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US 5,511,173 AGranted
Programmable logic array and data processing unit using the same
AssigneeRicoh Company, Ltd.
InventorsShinichi Yamaura, Takashi Yasui, Keiichi Yoshioka
Life of this patent
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Abstract
A programmable logic array includes a plurality of AND planes. Each AND plane executes an AND logic operation and has input terminals and output terminals. The programmable logic array also includes a single OR plane provided in common for the plurality of AND planes. The single OR plane executes an OR logic operation and has input terminals coupled to the output terminals of the plurality of AND planes and output terminals. A data processing unit using the above programmable logic array is also provided.
Claims24
A programmable logic array comprising:
- a plurality of AND planes, wherein each of said plurality of AND planes is activated by a respectively different precharge signal functioning as an enable signal to execute an AND logic operation, and has input terminals receiving respectively different code input signals than the other AND planes and output terminals;
- and
- a single OR plane, to which the plurality of AND planes are connected, provided in common for said plurality of AND planes and executing an OR logic operation, said single OR plane having input terminals coupled to said output terminals of said plurality of AND planes and output terminals.
A data processing unit comprising:
- a PLA (programmable logic array) circuit which receives information supplied from an external device and outputs a decoded signal;
- interface means, coupled to said PLA circuit, for generating a control signal from said decoded signal;
- and
- operation means, coupled to said interface means and having an arithmetic logic unit, for carrying out an operation on data on the basis of said control signal,
- wherein said PLA circuit comprises:
- a plurality of AND planes, wherein each of said plurality of AND planes is activated by a respectively different precharge signal functioning as an enable signal to execute an AND logic operation on said information, and has input terminals receiving respectively different code input signals than the other AND planes and output terminals;
- and
- a single OR plane to which the plurality of AND planes are connected, provided in common for said plurality of AND planes and executing an OR logic operation on signals output from said AND planes, said single OR plane having input terminals coupled to said output terminals of said plurality of AND planes, and output terminals through which said decoded signal is output.
5 more elements
A data processing unit comprising:
- a PLA (programmable logic array) circuit which receives information supplied from an external device and outputs a decoded signal;
- interface means, coupled to said PLA circuit, for generating a control signal from said decoded signal;
- and
- operation means, coupled to said interface means and having an arithmetic logic unit, for carrying out an operation on data on the basis of said control signal;
- wherein said information is in one of at least three different formats corresponding to at least three different addressing modes;
- and
- wherein said PLA circuit comprises predecoded means for determining the format of said information and operating in a corresponding one of at least three different addressing modes, and a plurality of AND planes connected to a single OR plane, each of said plurality of AND planes receiving respectively different code input signals and being activated by a respectively different precharge signal functioning as an enable signal.
4 more elements
A data processing unit comprising:
- a PLA (programmable logic array) circuit which receives information supplied from an external device and outputs a decoded signal;
- interface means, coupled to said PLA circuit, for generating a control signal from said decoded signal;
- and
- operation means, coupled to said interface means and having an arithmetic logic unit, for carrying out an operation on data on the basis of said control signal;
- wherein said information is in one of at least three different formats corresponding to at least three different addressing modes,
- wherein said PLA circuit comprises predecoded means for determining the format of said information and operating in a corresponding one of at least three different addressing modes, and a plurality of AND planes, each of said plurality of AND planes receiving respectively different input signals;
- and
- wherein each of the plurality of AND planes is synchronized with a corresponding clock signal which is controlled independently of the other clock signals.
5 more elements
A programmable logic array comprising:
- a plurality of AND planes, each executing an AND operation and having input terminals receiving different input signals than the other AND planes and output terminals:
- and
- a single OR plane provided in common for said plurality of AND planes and executing an OR logic operation, said single OR plane having input terminals coupled to said output terminals of said plurality of AND planes and output terminals,
- wherein each of the plurality of AND planes is synchronized with a corresponding clock signal which is controlled independently of the other clock signals.
1 more element
A data processing unit comprising:
- a PLA (programmable logic array) circuit which receives information supplied from an external device and outputs a decoded signal;
- interface means, coupled to said PLA circuit, for generating a control signal from said decoded signal;
- and
- operation means, coupled to said interface means and having an arithmetic logic unit, for carrying out an operation on data on the basis of said control signal,
- wherein said PLA circuit comprises:
- a plurality of AND planes, each executing an AND logic operation on said information and having input terminals receiving different input signals than the other AND planes and output terminals;
- and
- a single OR plane provided in common for said plurality of AND planes and executing an OR logic operation on signals output from said AND planes, said single OR plane having input terminals coupled to said output terminals of said plurality of AND planes, and output terminals through which said decoded signal is output,
- and wherein each of the plurality of AND planes is synchronized with a corresponding clock signal which is controlled independently of the other clock signals.
6 more elements
Dependencies are inferred from the claim text.