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US 5,511,154 AGranted
Method and apparatus for managing concurrent access to multiple memories
AssigneeInternational Business Machines Corporation
InventorsLee E. Johnson, Jr., Daryl J. Kokoszka, Steven P. Larky
Life of this patent
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Abstract
A memory apparatus includes a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and the receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, concurrently accessing at least one remaining buffer.
Claims18
A data processing apparatus comprising:
- a plurality of processing means;
- storage means for receiving and serially storing a plurality of instructions from said plurality of processing means;
- a plurality of buffer memories, each buffer memory storing different types of data:
- a plurality of buffer control means, each of said buffer control means coupled to a corresponding one of said buffer memories for regulating access to that corresponding buffer memory for any of said plurality of processing means;
- memory management means, connected to each of said buffer control means and to said storage means, for accessing a first instruction from a first one of said processing means and a second one of said plurality of instructions from said storage means from a second one of said processing means, and
- for obtaining from one or more of said buffer control means access to at least one first corresponding buffer memory in response to said first accessed instruction from said first processing means and updating at least one of said first corresponding buffer memory dependent upon a value previously stored in at least one of the accessed first corresponding buffer memory
- while, in response to said second instruction from said second processing means, concurrently obtaining from at least one buffer control means not currently accessed, access to at least one second corresponding buffer memory not currently accessed and updating at least one of said second corresponding buffer memories dependent upon a value previously stored in at least one of the accessed second corresponding buffer memories.
4 more elements
A method for controlling access of information in a memory apparatus comprising the steps of:
- receiving from a plurality of processing means and serially storing a plurality of instructions in a storage means;
- regulating access for any of said plurality of processing means to each of a plurality of buffers, each buffer storing different types of data;
- accessing a first instruction from a first one of said processing means and a second instruction from a second processing means from the storage means;
- and
- obtaining access to one or more of said buffers in response to said first accessed instruction from said first one of said processing means and updating at least one of said first corresponding buffer memory dependent upon a value previously stored in at least one of the accessed first corresponding buffer memory while, in response to said second instruction, concurrently obtaining access to at least one buffer not already accessed and updating at least one of said second corresponding buffer memory dependent upon a value previously stored in at least one of the accessed second corresponding buffer memory.
2 more elements
A data processing system comprising:
- a main processor;
- a plurality of processing means for processing data under instruction of said main processor;
- storage means for receiving and serially storing a plurality of instructions from said plurality of processing means;
- a plurality of buffer memories, each buffer memory storing different types of data;
- a plurality of buffer control means, each of said buffer control means coupled to a corresponding one of said buffer memories for regulating access to that corresponding buffer memory for any of said plurality of processing means;
- memory management means, connected to each of said buffer control means and to said storage means, for accessing through said storage means a first instruction from a first one of said processing means and a second instruction from a second one of said processing means, and
- for obtaining from one or more of said buffer control means access to at least one of first corresponding buffer memory in response to said first instruction from said first processing means and updating at least one of said first corresponding buffer memory dependent upon a value previously stored in at least one of the accessed first corresponding buffer memory
- while, in response to said second instruction from said second processing means, concurrently obtaining from at least one buffer control means not currently accessed, access to at least one second corresponding buffer memory not currently accessed and updating at least one of said second corresponding buffer memory dependent upon a value previously stored in at least one of the accessed second corresponding buffer memory.
5 more elements
Dependencies are inferred from the claim text.