Phase-locked loop synthesizer

A phase-locked loop (PLL) circuit for producing an oscillation frequency signal having an oscillation frequency that is phase-locked with a reference frequency signal having a predetermined reference frequency, comprising:

• variable frequency oscillation means outputting the oscillation frequency signal (fo);
• pulse train generating means receiving said oscillation frequency signal as a clock signal, said pulse train generating means converting a train of n clock signals to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses having non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that said pulses having the non-uniform numbers of clocks are arranged differently;
• phase comparing means outputting a phase error signal by determining a phase error between said reference frequency signal and said oscillation frequency signal based on said reference frequency (fr) signal and said m sequential pulse trains;
• and
• filtering means filtering said phase error signal to produce a frequency control signal, and providing said frequency control signal to said variable frequency oscillation means;
• said oscillation frequency (fo) being expressed as fo=n.times.(fr/m) where fr is the reference frequency.

A phase-locked loop (PLL) circuit for producing an oscillation frequency signal having an oscillation frequency that is phase-locked with a reference frequency signal having a predetermined reference frequency, comprising:

• variable frequency oscillation means outputting the oscillation frequency signal (fo);
• pulse train generating means receiving said oscillation frequency signal as a clock signal, said pulse train generating means converting a train of n clock signals to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses having non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that said pulses having the non-uniform numbers of clocks are arranged differently;
• phase comparing means outputting a phase error signal by determining a phase error between said reference frequency signal and said oscillation frequency signal based on said reference frequency (fr) signal and said m sequential pulse trains;
• and
• filtering means filtering said phase error signal to produce a frequency control signal, and providing said frequency control signal to said variable frequency oscillation means, said filtering means has a time constant suppressing a component of said reference frequency.

A phase-locked loop (PLL) circuit for producing an oscillation frequency signal having an oscillation frequency that is phase-locked with a reference frequency signal having a predetermined reference frequency, comprising:

• variable frequency oscillation means outputting the oscillation frequency signal (fo);
• pulse train generating means receiving said oscillation frequency signal as a clock signal, said pulse train generating means converting a train of n clock signals to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses having non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that said pulses having the non-uniform numbers of clocks are arranged differently;
• said pulse train generating means includes;
• a first flip-flop receiving said oscillation frequency signal as the clock signal, for taking in a selected output of a selector;
• an adder for adding m to an output of said first flip-flop;
• a subtracter for subtracting n from the output of said adder;
• a selector for selecting the output of said adder when the output of said subtracter is negative, and selecting the output of said subtracter when the output of said subtracter is zero or positive, and supplying the selected output to said first flip-flop;
• and
• m numerical comparators comparing the output of said first flip-flop with m different thresholds, and outputting said m sequential pulse trains;
• phase comparing means outputting a phase error signal by determining a phase error between said reference frequency signal and said oscillation frequency signal based on said reference frequency (fr) signal and said m sequential pulse trains;
• and
• filtering means filtering said phase error signal to produce a frequency control signal, and providing said frequency control signal to said variable frequency oscillation means.

A phase-locked loop (PLL) circuit for producing an oscillation frequency signal having an oscillation frequency that is phase-locked with a reference frequency signal having a predetermined reference frequency, comprising:

• variable frequency oscillation means outputting the oscillation frequency signal (fo);
• pulse train generating means receiving said oscillation frequency signal as a clock signal, said pulse train generating means converting a train of n clock signals to m pulses where n and m are positive integers, generating sequential pulses produced by arranging part of the m pulses having non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that said pulses having the non-uniform numbers of clocks are arranged differently;
• said pulse train generating means includes;
• a first flip-flop receiving said oscillation frequency signal as the clock signal, for taking in a selected output of a selector;
• a subtracter for subtracting m from an output of said first flip-flop;
• an adder for adding n to an output of said subtracter;
• a selector for selecting the output of said subtracter when the output of said adder is larger than n, and selecting a value obtained by adding n from the output of said adder when the output of said adder is not larger than n, and supplying the selected output to said first flip-flop;
• and
• m numerical comparators for comparing the output of said first flip-flop with m different thresholds, and outputting said m sequential pulse trains;
• phase comparing means for outputting a phase error signal by determining a phase error between said reference frequency signal and said oscillation frequency signal based on said reference frequency (fr) signal and said m sequential pulse trains;
• and
• filtering means for filtering said phase error signal to produce a frequency control signal, and providing said frequency control signal to said variable frequency oscillation means.

A phase-locked loop (PLL) circuit for producing an oscillation frequency signal having an oscillation frequency that is phase-locked with a reference frequency signal having a predetermined reference frequency, comprising:

• variable frequency oscillator outputting the oscillation frequency signal (fo);
• pulse train generator receiving said oscillation frequency signal as a clock signal, said pulse train generator converting a train of n clock signals to m pulses where n and m are positive integers, and generating sequential pulses produced by arranging part of the m pulses having non-uniform numbers of clocks, and outputting m periodical, sequential pulse trains so that timing of said m pulses produced by different numbers of clocks divided from said n clock signals are arranged non-uniformly;
• phase comparator outputting a phase error signal by determining said phase error signal between said reference frequency signal and said m sequential pulse trains, respectively, and by combining respective phase error signals;
• and
• a filter which filters said phase error signal to produce a frequency control signal, and provides said frequency control signal to said variable frequency oscillator.