Method and apparatus for performing frequency detection

In a system having a clock generator for generating a reference clock signal and an oscillator for performing frequency synthesis, a frequency detector for comparing a frequency of the reference clock signal to an oscillator output signal, said frequency detector comprising:

• enable circuitry, coupled to said oscillator, for receiving the reference clock signal and a start signal, and providing an enable signal, in response thereto., to force said oscillator to generate said oscillator output signal synchronously with the reference clock signal;
• counter circuitry for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and for providing a count output signal indicating the number of signal transitions of said oscillator output signal,,
• a first counter for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, said first counter having an input for receiving said oscillator output signal and an output for providing said count output signal indicating whether the number of signal transitions of said oscillator output., relative to a predefined number of transitions of said reference clock signal, is less than or not less than a target number;
• and
• a reference clock counter for counting said predefined number of transitions of said reference clock signal, and for providing a reset signal to reset said first counter to an initial value;
• synchronization circuitry, coupled to said first counter and the enable circuitry, for receiving said count output signal and for generating, during a predefined reference clock interval, a set of binary signals indicating whether said number of signal transitions of said oscillator output signal is at least a predefined integer number, said enable circuitry resetting said first counter, said reference clock counter and said oscillator during said predefined reference clock interval;
• and
• a delay circuit, coupled to said enable circuitry, for matching a delay inherent in the first counter with a propagation delay relative to the reference clock signal.

In a system having a clock generator for generating a reference clock signal, an oscillator for performing frequency synthesis, a synchronization circuitry coupled to a counter, and enable logic circuitry coupled to said synchronization circuitry and said oscillator, a method for performing frequency detection comprising the steps of:

• forcing phase alignment of said oscillator output signal to said reference clock signal by enabling, via said enable logic circuitry said oscillator to generate said oscillator output signal , synchronously with the reference clock signal;
• serially counting, via said counter, a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and providing a count output signal indicating whether the number of signal transitions of said oscillator output signal is less than or not less than a target number;
• matching, via said enable logic circuitry, a delay inherent in the counter and the enable logic circuitry with a propagation delay relative to the reference clock signal;
• receiving, via said synchronization circuitry, said count output signal and generating, during a predefined reference clock interval, a first control signal, when said count output signal is less than said target number, or a second control signal when said count output signal is not less than said target;
• and
• resetting, via said enable logic circuitry, said counter circuitry and said oscillator during said predefined reference clock interval.