Signal processor for a sub-band coding system

A signal processor for a subband coding system comprising:

• selecting means receiving sample data, allocation information, and synchronization and system information during an encoding operation for changing said sample data to another form and thereby providing various data corresponding to said sample data, said allocation information and said synchronization and system information and for providing said sample data during a decoding operation;
• first storing means for temporarily storing said various data received from said selecting means during said encoding operation;
• operating means for selectively scaling and quantizing unencoded sample data to thereby produce operated data during said encoding operation and for dequantizing and descaling said operated data included in encoded data during said decoding operation;
• classifying means for selectively providing said operated data, said allocation information input to said operating means, and said synchronization and system information in accordance with a frame format for a general subband coding system as said encoded data during said encoding operation, and for receiving said encoded data and classifying said encoded data into said synchronization and system information, said allocation information and said operated data during said decoding operation;
• and
• control signal generating means for generating control signals for selectively controlling said encoding operation and said decoding operation performed by said selecting means, said storing means, said operating means and said classifying means.

A method for operating a signal processor for a subband coding system including:

• a selector receiving sample data, allocation information, and synchronization and system information during an encoding operation for providing various data corresponding to said sample data, said allocation information and said synchronization and system information and for providing said sample data during a decoding operation;
• a memory temporarily storing said various data during said encoding and said decoding operations;
• an operating circuit selectively scaling and quantizing unencoded sample data to thereby produce operated data and dequantizing and descaling said operated data included in encoded data, said operating circuit including a buffer temporarily storing sample data, a plurality of interim values and said operated data, a maximum absolute value calculator, a log circuit, a coefficient generator, an adder, an antilog circuit and a multiplier;
• a classifier selectively providing said operated data, said allocation information input to said operating means, and said synchronization and system information in accordance with a frame format for a general subband coding system as said encoded data during said encoding operation, and for receiving said encoded data and classifying said encoded data into said synchronization and system information, said allocation information and said operated data during said decoding operation;
• and a control signal generator generating control signals for selectively controlling said encoding operation and said decoding operation performed by said selector, said memory, said operating circuit and said classifier, said method comprising the steps of:
• encoding said sample data to produce operated data by the steps of:
• (a) calculating a first log value representing the maximum absolute values of a predetermined number of sample data using said log circuit;
• (b) calculating respective log values of said sample data;
• (c) arithmetically combining said first log values with said respective log values to thereby produce first interim values using said adder;
• (d) calculating respective antilog values of said respective first interim values using said antilog circuit;
• (e) adding a product of said respective antilog values and a first coefficient provided by said coefficient generator using said multiplier with a second coefficient from said coefficient generator using said adder to thereby produce said operated data;
• and
• decoding said operated data to provide said sample data by the steps of:
• (f) adding said operated data to a third coefficient using said adder to produce second interim data;
• (g) multiplying said second interim data with a value corresponding to a fourth coefficient plus an integer using said multiplier to produce a third interim value;
• (h) adding said second interim value to said third interim value to thereby produce a fourth interim value using said adder:
• (i) calculating a fourth log value using said log circuit;
• (j) combining said fourth log value and a value approximating said first log value using said adder to produce a fifth interim value;
• and
• (k) calculating said sample data using said antilog circuit.