Method and apparatus for controlling a communication device through a modem processor

Abstract

A method and apparatus for a processor of a computer system to control a communication device through a bus interface having six interconnects. The bus interface's first interconnect is a transmission and reception interconnect that allows the computer system to transmit and receive signals from a communication device (such as a telephone line or a radio transceiver). The second interconnect is a primary processor communication interconnect which serves as the primary communication route between the processor and a radio transceiver's microcontroller, and which enables the processor to control the various components of the radio transceiver. The third interconnect is a secondary processor communication interconnect that relays urgent signals (such as status, interrupt, and reset signals) between the processor and the radio transceiver's microcontroller. A received signal strength indicator interconnect is the fourth interconnect and it relays an analog signal specifying the strength of an incoming signal from the radio to the computer system. The fifth interconnect is a power supply link for supplying power signals to the radio transceiver. Finally, the sixth interconnect is a half-duplex control interconnect which allows the computer system to control the half-duplex nature of some radio transceivers.

Dependencies are inferred from the claim text.