Back to results
US 5,511,034 AGranted
Simple temporary information storage circuit controllable with enable/reset signal
AssigneeNEC Corporation
InventorYutaka Hirata
Life of this patent
Estimating the term…
Abstract
Only a flip flop circuit (11a), an n-channel enhancement type transfer transistor (Qn11) coupled between an input node and the flip flop (11a) and a p-channel enhancement type reset transistor (Qp12) coupled between a power voltage line (Vcc) and the flip flop circuit (11a) form in combination a temporary information storage circuit, and the n-channel enhancement type transfer transistor (Qn11) and the p-channel enhancement type reset transistor (Qp12) are respectively controlled by a latch control signal (CTL2) and an enable/reset signal (EBL2) for changing the status of the flip flop circuit.
Claims5
An addressing system comprising
- a plurality of address predecoder circuits for producing address predecoded signals from address bits indicative of a plurality of addresses in a time division multiplexing sequence,
- a first address decoder unit coupled to said plurality of address predecoders for producing first address decoded signals,
- a plurality of first temporary information storage circuits responsive to a first and a second control signals in a first phase for temporarily storing said first address decoded signals,
- a second address decoder unit coupled to said plurality of address predecoders for producing second address decoded signals, and
- a plurality of second temporary information storage circuits responsive to said first and second control signals in a second phase after said first phase for temporarily storing said second address decoded signals.
2 more elements
Dependencies are inferred from the claim text.