Hidden self-refresh method and apparatus for synchronous dynamic random access memory

In a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, a hidden self-refresh apparatus comprising:

• first input means for inputting an external first address signal for addressing any one of said cell banks;
• second input means for inputting an external second address signal for addressing any one of said cell arrays in said cell banks;
• counting means for generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to a logical value of said first address signal from said first input means;
• multiplexing means for selecting either said refresh address signal from said counting means or said second address signal from said second input means;
• and
• at least two latch means being individually driven according to the logical value of said first address signal from said first input means, each of said at least two latch means transferring the refresh or second address signals selected by said multiplexing means to a corresponding one of said cell banks.

In a synchronous dynamic random access memory having at least two cell banks, each of said cell banks including a plurality of cell arrays, a hidden self-refresh apparatus comprising:

• first input means for inputting an external first address signal for addressing said cell banks;
• second input means for inputting an external second address signal for addressing any one of said cell arrays in said cell banks;
• at least two counting means being individually driven according to a logical value of said first address signal from said first input means, each of said at least two counting means generating a refresh address signal for addressing any one of the plurality of cell arrays in one of said cell banks corresponding to the logical value of said first address signal from said first input means;
• multiplexing means for selecting either said refresh address signal from any one of said at least two counting means or said second address signal from said second input means;
• and
• at least two latch means being individually driven according to the logical value of said first address signal from said first input means, each of said at least two latch means transferring the refresh and second address signals selected by said multiplexing means to a corresponding one of said cell banks.