US 5,511,030 AGranted

Semiconductor memory device and method of driving same

AssigneeOki Electric Industry Co., Ltd.

InventorsYasuhiro Tanaka, Tetsuya Tanabe, Satoru Tanoi

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Abstract

A semiconductor memory device according to the present invention is constructed in such a manner that two first and second memory circuits are respectively electrically connected to one sense amplifier provided between the memory circuits through changeover elements and equalize elements are electrically connected to their corresponding bit line pairs included in the memory circuits. Owing to this construction, an operation for resetting the bit line pair in the first memory circuit and the sense amplifier after completion of access to the first memory circuit and an operation for reading data into the bit line pair in the second memory circuit can be performed so as to overlap each other in time. It is therefore possible to obtain quick-access to the second memory circuit.

Claims16

Dependent claims

A semiconductor memory device comprising:

a first memory circuit including a first word line, a first bit line pair intersecting said first word line and a memory cell connected to a point where said first word line and said first bit line pair intersect;
a second memory circuit including a second word line, a second bit line pair intersecting said second word line and a memory cell connected to a point where said second word line and said second bit line pair intersect;
a sense amplifier having a pair of nodes provided so as to correspond to said first bit line pair and to said second bit line pair and means for amplifying a differential voltage between said pair of nodes;
a reset circuit for resetting the voltages on the two nodes of said pair of nodes to a predetermined voltage;
a first changeover element for connecting said first bit line pair and said pair of nodes to one another;
a second changeover element for connecting said second bit line pair and said pair of nodes to one another;
a first equalization element connected to said first bit line pair, for setting said first bit line pair to a first equalization potential;
a second equalization element connected to said second bit line pair, for setting said second bit line pair to a second equalization potential;
a first drive circuit for turning off said first changeover element after an access to said memory cell in said first memory circuit;
a second drive circuit for activating said first equalization element after a deactivation of said first word line following the turning off of said first changeover element;
a third drive circuit for causing a first operation for deactivating said first word line and a second operation overlapping the first operation in time, for activating said first equalization element after the turning off of said first changeover element, and for activating said reset circuit for resetting the voltages on the two nodes of said pair of nodes to the predetermined voltage;
a fourth drive circuit for activating said second equalization element for setting said second bit line pair to the second equalization potential to enable information stored in said second memory circuit to be transferred to said second bit line pair;
a fifth drive circuit for driving said second changeover element to transfer information stored in said memory cell in said second memory circuit to said pair of nodes after said pair of nodes has been reset;
a sixth drive circuit for driving said sense amplifier to amplify the differential voltage between the two nodes of said pair of nodes;
and
detecting means for detecting that said second memory circuit has been selected after the selection of said first memory circuit, and adapted to independently control said first, second, third, fourth, fifth and sixth drive circuits.

13 more elements

A semiconductor memory device comprising:

a first memory circuit including a first word line and a first pair of bit lines;
a second memory circuit including a second word line and a second pair of bit lines;
a sense amplifier having a pair of nodes provided so as to correspond to the first and second pairs of bit lines and means for amplifying a differential voltage between the pair of nodes;
a reset circuit for resetting the pair of nodes to a predetermined voltage;
a first switching circuit for connecting the first pair of bit lines and the pair of nodes to each other;
a second switching circuit for connecting the second pair of bit lines and the pair of nodes to each other;
a first equalization circuit coupled to the first pair of bit lines for setting both of the first pair of bit lines to a first equalization potential;
a second equalization circuit coupled to the second pair of bit lines for setting both of the second pair of bit lines to a second equalization potential;
and
a detecting circuit, coupled to said first and second memory circuits, said sense amplifier, said reset circuit, said first and second switching circuits and said first and second equalization circuits, for activating said first memory circuit, said sense amplifier, said first switching circuit and said second equalization circuit while deactivating said second memory circuit, said reset circuit, said second switching circuit and said first equalization circuit during a first period of time, and for activating said second memory circuit, said sense amplifier, said second switching circuit and said first equalization circuit while deactivating said first memory circuit, said reset circuit, said first switching circuit and said second equalization circuit during a second period of time which is nonoverlapping with respect to the first period of time.

7 more elements

A semiconductor memory device comprising:

a first memory circuit including a first word line and a first pair of bit lines, said first memory circuit being activated during a first period of time;
a second memory circuit including a second word line and a second pair of bit lines, said second memory circuit being activated in a second period of time which is nonoverlapping with respect to the first period of time;
a sense amplifier having a pair of nodes corresponding to the first pair of bit lines and further corresponding to the second pair of bit lines, and having means for amplifying a differential voltage between the pair of nodes, said sense amplifier being activated during the first and second periods of time;
a reset circuit for resetting the pair of nodes to a predetermined voltage, said reset circuit being deactivated during the first and second periods of time;
a first switching circuit for connecting the first pair of bit lines to the pair of nodes, said first switching circuit being activated during the first period of time;
a second switching circuit for connecting the second pair of bit lines to the pair of nodes, said second switching circuit being activated during the second period of time;
a first equalization circuit coupled to the first pair of bit lines for setting both of the first pair of bit lines to a first equalization potential, said first equalization circuit being activated during the second period of time;
and
a second equalization circuit coupled to the second pair of bit lines for setting both of the second pair of bit lines to a second equalization potential, said second equalization circuit being activated during the first period of time.

6 more elements

Dependencies are inferred from the claim text.