Test circuit in clock synchronous semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsSeiji Sawada, Yasuhiro Konishi
Life of this patent
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Abstract
In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.
Claims33
A synchronous semiconductor memory device taking in external signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor device comprising:
- a data output terminal;
- read means for simultaneously reading data from a predetermined plurality of memory cells in response to a read mode command incorporated in synchronization with said clock signal for successively transferring said data to said data output terminal;
- and
- compression means for carrying out a prescribed logical operation on said data read by said read means from said plurality of memory cells in response to a test mode designating signal for compressing said data to one-bit data and externally outputting the same.
A synchronous semiconductor memory device incorporating external signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:
- a plurality of data output terminals;
- a plurality of read means provided corresponding to said plurality of data output terminals for simultaneously reading data from a predetermined plurality of memory cells in response to a read mode command incorporated in synchronization with said clock signal each for successively transferring said data to a corresponding data output terminal in response to said clock signal;
- a plurality of compression means each provided corresponding to a respective read means for carrying out a prescribed logical operation on said data read by a corresponding read means from said predetermined plurality of memory cells thereby compressing said data to one-bit data;
- and
- output means for generating outputs of each respective compression means to said corresponding data output terminal.
A synchronous semiconductor memory device incorporating external signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:
- a plurality of data output terminals;
- a plurality of read means provided corresponding to said plurality of data output terminals for simultaneously reading data from a predetermined plurality of memory cells in response to a read mode command incorporated in synchronization with said clock signal;
- compression means for carrying out a prescribed logical operation on said data read by said plurality of read means from said memory cells for compressing said data to one-bit data;
- and
- output means for generating an output of said compression means to a particular one of said plurality of data output terminals.
A synchronous semiconductor memory device incorporating external signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:
- a plurality of banks each having a memory cell array;
- activation means provided for the plurality of banks for activating and precharging each memory array of said plurality of banks on a bank by bank basis;
- a data output terminal provided in common for said plurality of banks;
- read means provided for each of said plurality of banks for simultaneously reading data from a predetermined plurality of memory cells of the memory cell array corresponding to one of said plurality of banks in response to a read mode command incorporated in synchronization with said clock signal for successively transferring said data to said data output terminal in response to said clock signal;
- a plurality of first compression means provided corresponding to the banks and each said first compression means for carrying out a prescribed logical operation on said data read by corresponding read means from said plurality of memory cells in an activated bank for compressing said data to one-bit data;
- and
- second compression on outputs for carrying out another prescribed logical operation on outputs of said plurality of first compression means for compressing said outputs to one-bit data and externally outputting the same to said data output terminal.
A synchronous semiconductor memory device incorporating external signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:
- a plurality of banks each having a memory cell array;
- activation means provided corresponding to the banks and for activating and precharging corresponding memory arrays, on a bank by bank basis;
- a plurality of data output terminals shared by said plurality of banks;
- a plurality of read means provided corresponding to said plurality of data output terminals in each said bank for simultaneously reading data from a predetermined plurality of memory cells of the memory cell array corresponding to one of said plurality of banks in response to a read mode command incorporated in synchronization with said clock signal for successively transferring said data to said plurality of data output terminals in response to said clock signal;
- a plurality of first compression means provided corresponding to the respective banks for carrying out a first logical operation on said data read by each of said plurality of read means from said predetermined plurality of memory cells in each said bank for compressing said data to one-bit data;
- and
- second compression means for carrying out a second logical operation on outputs of said plurality of first compression means for compressing said outputs to one-bit data and externally outputting the same.
A synchronous semiconductor memory device incorporating external signals including address signals and control signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:
- a plurality of banks each including a memory cell array with each memory cell array having a plurality of memory cells, each bank including means for selecting a memory cell designated by an address signal incorporated in synchronization with said clock signal;
- first activation means responsive to a bank address signal designating a bank incorporated in synchronization with said clock signal for activating a bank designated by said bank address signal, independently of the states of activation and precharging of remaining banks in a normal mode of operation, and
- second activation means for simultaneously activating said plurality of banks in response to a test mode designating signal.
A semiconductor memory device incorporating external signals including address signals and control signals in synchronization with a clock signal formed of a series of pulses, said synchronous semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells;
- read means for simultaneously reading data of a prescribed number of memory cells from said memory cell array;
- a first wired circuit having a plurality of n-channel insulated gate type field effect transistors each having a gate receiving each respective data read by said read means from said prescribed number of memory cells, said plurality of n-channel insulated gate type field effect transistors being connected between a first signal line and a first potential node in parallel with each other;
- a second wired circuit provided separately from said first wired circuit and having a plurality of p-channel insulated gate type field effect transistors each having a gate receiving each respective data read by said read means from said prescribed number of memory cells, said p-channel insulated gate type field effect transistors connected between a second signal line and a second potential node in parallel with each other;
- and
- logic means coupled to receive signals on said first and second signal lines for carrying out a prescribed logic operation on outputs of said first and second wired circuits.
A synchronous type semiconductor memory device operating in synchronization with a clock signal, comprising:
- data output means for externally supplying received data in synchronization with said clock signal;
- a memory cell array having a plurality of memory cells;
- selection means responsive to an address signal received in synchronization with said clock signal for simultaneously selecting a predetermined number of said memory cells in said memory cell array,
- said predetermined number being a multiple of a number of data bits which said data output means can externally supply at a time;
- read means responsive to a read mode designating signal received in synchronization with said clock signal for simultaneously reading and storing data of said predetermined number of memory cells selected by said selection means;
- and
- compression means responsive to a test mode designating signal designating a test mode of operation for compressing the data of the predetermined number of cells stored in said read means to a one-bit data indicating whether or not a defective memory cell is included in said predetermined number of memory cells for external outputting.
Dependencies are inferred from the claim text.