Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsLee E. Cleveland, Shane C. Hollmer
Estimating the term…
A gate power supply for supplying power to the gates of flash EEPROM memory cells in a multi-density or low voltage supply memory array to determine the states stored by the memory cells. The gate power supply includes a multi-phase voltage pump to increase voltage supplied to the gates of the memory cells above a system voltage supply, V.sub.CC to increase the working margin between memory cell states. The gate power supply further includes a low power supply standby pump to maintain the boosted voltage during an inactive mode. The wordline decoder for the memory is divided into sections with a large n-well parasitic capacitance of each decoder section acting as a reservoir to store the charge supplied by the low power standby pump. In an active mode, the parasitic capacitance in unselected decoder sections supplies power to the input of the selected diecoder section while the multi-phase pump is turning on. Zener regulation diodes are coupled to the inputs of each decoder section to regulate the voltage supplied to each section. A reference supply feeds back power from the input of the selected decoder section to the input of a reference array. The reference supply further provides circuitry to reduce mismatches between the memory array and the reference array.
A gate power supply for supplying power to a gate of an array cell in a memory array, the memory array being programmable using a verify cycle to verify programming of a given state in a plurality of possible states stored by the array cell and readable using a read cycle to read the given state of the array cell once the verify cycle is complete, the gate power supply connected to a power supply output, the power supply output connectable for providing a first power supply signal, Vcc, having a given magnitude, wherein if the first power supply signal was provided to the gate of the array cell, a working margin would exist between the plurality of possible states, the gate power supply comprising:
A gate power supply for supplying power to wordlines of a flash EEPROM memory array to determine thresholds of array cells connected to the wordlines, the gate power supply connecting to a power supply output, the power supply output connectable for providing a first power supply signal (Vcc), the gate power supply comprising:
Dependencies are inferred from the claim text.