Write per bit with write mask information carried on the data path past the input data latch
AssigneeTexas Instruments Incorporated
InventorsScott E. Smith, Duy-Loan T. Le, Michael Ho
Life of this patent
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Abstract
A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.
Claims9
A dynamic random access memory device formed on a substrate of semiconductor material and providing a write per bit feature, the device comprising:
- a semiconductor component;
- a data path on the substrate that extends from a data bond pad through the semiconductor component to an input-output buffer for exchanging data signals between the bond pad and the input-output buffer;
- and
- a write mask latch coupled to the data path, the write mask latch receiving mask write information applied to the bond pad and transmitted on the data path through the semiconductor component, the write mask latch coupled to the input-output buffer for controlling transmission of data signals therethrough.
A process of effecting a write per bit feature in writing data on a data path from a bond pad through a semiconductor component to a memory cell in a dynamic random access memory device, the process comprising the steps of:
- a. writing write mask information across the data path from the bond pad through the semiconductor component to, a mask register the mask reqister coupled to the data path for controlling data transmitted thereon;
- and
- b. writing data on the data path through the semiconductor element and to the memory cell in response to the write mask information contained in the mask latch.
Apparatus for implementing a write per bit feature in a dynamic random access memory unit;
- the dynamic random access memory unit having an input register, an intermediate buffer, and a memory cell;
- the apparatus comprising:
- a write mask latch coupled to an output terminal of the intermediate buffer for storing write mask information therein;
- and
- a local I/O buffer coupled between the intermediate buffer and the memory cell, the local I/O buffer responsive to the write mask information in the write mask latch for controlling the transfer of data from the local I/O buffer to the memory cell.
Dependencies are inferred from the claim text.