Depletion mode NAND string electrically erasable programmable semiconductor memory device and method for erasing and programming thereof

An electrically erasable programmable semiconductor memory device, comprising:

• a plurality of bit lines arranged in columns;
• a plurality of memory strings arranged in columns, each memory string having a string selecting transistor, a plurality of floating-gate transistors and a ground selection transistor with respective drain-source paths coupled in series;
• a memory cell array wherein a drain of the string selection transistor and a source of the ground selection transistor in each memory string of the same column, are each coupled with the bit line and the ground of a corresponding column, and wherein a gate of the string selection transistor, each control gate of the floating-gate transistors and a gate of the ground selection transistor in each memory string of the same row, are respectively coupled with a string selection line, word lines and a ground selection line;
• row selection means coupled to the string selection line, the word lines and the ground selection line from memory strings of each row, for applying a ground voltage to a selected word line coupled to the memory strings in a row according to an input row address during a program operation, and for applying a pass voltage to unselected word lines between said selected word line and a string selection line of the particular memory string, and to said string selection line;
• column selection means coupled between each bit line and a data line, for electrically connecting said selected bit line to said data line according to an input column address during a program operation;
• precharge means coupled with each bit line, for precharging each bit line with an erase prevention voltage in response to a precharge signal during the program operation;
• and
• program control means coupled to said data line, for providing said selected bit line with one of a program voltage and an erase prevention voltage in response to input data, upon the program operation, wherein during the program operation, a given voltage is applied to the unselected word lines between said selected word line and the ground selection line of the particular memory strings, and the ground voltage is applied to said ground selection line, and wherein said program control means comprises:
• a gate for providing first and second logic signals in response to the input data and said precharge signal;
• a first transistor having drain-source path connected between said data line and a program voltage terminal;
• a second transistor having drain-source path connected between said data line and an erase prevention voltage terminal;
• high-voltage switching means coupled between said gate and a gate of the first transistor, for enabling conduction of said first transistor in response to said first logic signal;
• and
• an AND gate coupled between said gate and a gate of the second transistor, for enabling conduction of said second transistor in response to said second logic signal and said precharge signal.

An electrically erasable programmable semiconductor memory device, comprising:

• a plurality of bit lines arranged in columns;
• a plurality of memory strings arranged in columns and connected to said plurality of bit lines respectively, each memory string having a string selection transistor, a plurality of floating-gate depletion-type transistors representing memory cells, and a ground selection transistor with respective drain-source paths coupled in series, each of said floating-gate depletion-type transistors exhibiting a negative virgin threshold voltage and being formed by a P-type well region formed on a N-type substrate comprising a source region and a drain region separated and spaced-apart by a channel region implanted by N-type impurities;
• a string selection line connected to the string selection transistor of each memory string;
• a plurality of word lines connected to said plurality of floating-gate depletion-type transistors of each memory string, respectively;
• a ground selection line connected to the ground selection transistor of each memory string;
• row selection means coupled to the string selection line, the word lines and the ground selection line from the memory strings of each row, for applying a given voltage according to one of erase, program and read operations to selected word lines and unselected word lines, the string and ground selection lines in a single row of the memory strings according to an input address;
• precharge means coupled with said each bit line, for precharging unselected bit lines with an erase prevention voltage during the program operation;
• and
• back-bias generator means for generating a back-bias voltage to said P-type well region of the memory cells during the read operation, said back-bias generator means comprising:
• charge pump means for generating said back-bias voltage during the read operation;
• back-bias control means for controlling said back-bias voltage at a constant level;
• and
• back-bias discharge means for inhibiting generation of said back-bias voltage during the erase and program operations.

In an electrically erasable programmable semiconductor memory device having a memory cell array including a plurality of bit lines in columns and a plurality of memory strings arranged in columns and connected to said bit lines respectively, each of said memory strings comprising a plurality of the memory cells connected to a corresponding bit line, each memory cell being a depletion-type N-MOS transistor exhibiting a negative virgin threshold voltage, said memory cell comprising:

• a substrate of a first conductivity type;
• a well region of a second conductivity type formed on said substrate, said well region accommodating application of a back-bias voltage to prevent leakage current flowing via a channel region of said memory cell during a data read operation;
• drain and source regions formed on said well region, said drain and source regions being separated and spaced-apart from each other by said channel region exhibiting impurities of said first conductivity type from one of arsenic and phosphorous to minimize inter-memory cell disturbance;
• a first insulation layer formed on said channel region and an edge portion of the drain region;
• a floating gate region formed on said first insulation layer and extended to overlap said edge portion of said drain region;
• a second insulation layer formed on said floating gate;
• and
• a control gate region formed on said second insulation layer.

An electrically erasable programmable semiconductor memory device, comprising;

• a plurality of bit lines arranged in columns;
• a plurality of memory strings arranged in columns and connected to said plurality of bit lines respectively, each memory string having a string selection transistor, a plurality of floating-gate depletion-type transistors representing memory cells, and a ground selection transistors with respective drain-source paths coupled in series, each of said floating-gate depletion-type transistors exhibiting a negative virgin threshold voltage and being formed by a P-type well region on a N-type substrate comprising a source region and a drain region separated and spaced-apart by a channel region implanted by N-type impurities;
• a string selection line connected to the string selection transistor of each memory string;
• a plurality of word lines arranged in rows and connected to said plurality of floating-gate depletion-type transistors of each memory string, respectively;
• a ground selection line connected to the ground selection transistor of each memory string;
• and
• row selection means coupled to the string selection line, the word lines and the ground selection line from the memory strings of each row, for applying a given voltage according to one or erase, program and read operations to selected word lines and unselected word lines, the string and ground selection lines in a single row of the memory strings according to an input address;
• precharge means coupled with each bit line, for precharging unselected bit lines with an erase prevention voltage during the program operation to prevent over-erase of memory cells;
• and
• back-bias generator means for supplying a back-bias voltage to said P-type well region of memory cells during the read operation to prevent leakage current.

An electrically erasable programmable semiconductor memory device, comprising:

• a plurality of bit lines arranged in columns;
• a plurality of word lines arranged in rows;
• a plurality of memory strings arranged in columns and connected to said plurality of bit lines respectively, each memory string comprising a string selection transistor, a plurality of floating-gate transistors connected to said plurality of word lines, and a ground selection transistor with respective drain-source paths coupled in series forming a memory cell array, wherein each floating gate transistor is a N-channel MOS memory cell comprising a N-type semiconductor substrate, a P-type well region formed on said N-type semiconductor substrate, a channel region implanted with N-type impurities, positioned between a source region and a drain region and formed on said P-type well region;
• a data line;
• column decoder means coupled to said data line and said bit lines, for selecting one of the memory strings arranged in columns in accordance with an input column address;
• precharge means coupled with said bit lines, for precharging unselected bit lines with an erase prevention voltage during a program operation to prevent over-erasure of memory cells;
• program control means coupled to said data line, for providing a program voltage to said data line during said program operation;
• latch means coupled with said bit lines, for latching said bit lines connected to selected word lines to a given voltage prior to an erase operation;
• and
• back-bias generator means for applying a back-bias voltage to said P-type well region of selected memory cells during a read operation to prevent leakage current;
• and
• row selection means coupled to the string selection line, the word lines and the ground selection line from each memory string of each row, for selecting ones of the word lines in a memory string in accordance with an input row address and enabling execution of said erase operation, said program operation and said read operation.

An electrically erasable programmable semiconductor memory device, comprising:

• p1 a plurality of bit lines arranged in columns;
• a plurality of word lines arranged in rows;
• a plurality of memory strings arranged in columns, each memory string comprising a string selecting transistor connected to respective bit line, a plurality of floating-gate transistors and a ground selection transistor with respective drain-source paths coupled in series forming a memory cell array, each floating-gate transistor representing a N-channel MOS memory cell comprising a control gate connected to respective word line, a P-type well region formed on a N-type semiconductor substrate, a channel region implanted with N-type impurities, positioned between a source region and a drain region and formed on said P-type well region;
• row selection means coupled to the string selection line, the word lines and the ground selection line from the memory strings connected to each row, for making selection of word lines in rows according to an input row address;
• column selection means coupled to said bit lines and a data line, for making selection of bit lines in columns according to an input column address;
• precharge means coupled to said bit lines, for precharging unselected bit lines with an erase prevention voltage during said program operation;
• program control means coupled to said data line, for providing said selected bit line with one of a program voltage and said erase prevention voltage during said program operation;
• and
• back-bias generator means for applying a back-bias voltage to said P-type well region of selected memory cells during a read operation to prevent leakage current.

A semiconductor memory device, comprising:

• a plurality of bit lines arranged in columns;
• a plurality of word lines arranged in rows;
• a plurality of memory strings arranged in columns each comprising a string selecting transistor, a plurality of floating-gate transistors and a ground selection transistor with respective drain-source paths coupled in series forming a memory cell array, each floating-gate transistor representing a N-channel MOS memory cell exhibiting a negative threshold voltage and comprising a control gate connected to respective word line and positioned on a P-type well region formed on a N-type semiconductor substrate, a channel region implanted with N-type impurities, positioned between a source region and a drain region and formed on said P-type well region, wherein said P-type well region accommodates application of a back-bias voltage to prevent leakage current flowing via said channel region during reading of selected memory cells;
• means for making selection of word lines in rows and for making selection of bit lines in columns according to input addresses;
• operation means for erasing all memory cells coupled a selected word line in a single row by applying an erase voltage to said selected word line, grounding all the bit lines, and applying a power voltage to the unselected word lines of respective memory string, and for alternatively erasing all memory cells coupled to all word lines by grounding all the bit lines and the ground selection line, applying said power voltage to the string selection line, and applying said erase voltage to all word lines.