Low power consumption type one-chip microcomputer having a plurality of peripheral circuits

A microcomputer comprising:

• a central processing unit;
• a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits;
• selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit;
• and
• means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits,
• wherein said selection means includes memory means for holding selection information indicative of use or non-use of each of said peripheral circuits, said memory means supplying said selection signal to each of said peripheral circuits on the basis of the selection information held in said memory means, and
• at least one external terminal connected to said memory means for writing said selection information into said memory means only at a time of resetting the microcomputer.

A microcomputer comprising:

• a central processing unit;
• a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits;
• selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit;
• and
• means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits,
• wherein said selection means comprises at least one external terminal and wherein said controlling means comprises an AND gate for receiving a first input from said at least one external terminal and for receiving a second input from a clock generating circuit, and
• wherein said AND gate is selectively placed in one of an open condition and a closed condition based on said first and second inputs.