Method and apparatus for logic simulation of logic system including multi-port memory

A logic simulation apparatus for evaluating a logic system including a multi-port memory having a plurality of independently addressable ports, each of which is one of input and output ports, by use of logic simulation, comprising:

• model creation means for constructing each of the input and output ports of said multi-port memory in a simulation model form using a corresponding plurality of memory primitives, said model creation means including:
• (1) base address setting means for setting said plurality of memory primitives representing the input and output ports of said multi-port memory to have a common base address, and
• (2) logic primitive creation means for creating logic primitives for effecting preset logic processes in connection with said respective memory primitives having said common base address, said logic primitive creation means including means for creating one of the logic primitives for transmitting an occurrence of a write operation of a memory primitive representing an input port to a memory primitive representing an output port;
• and
• simulation means for evaluating the logic system using the constructed simulation model according to an event-driven simulation only when a status variation occurs in said logic system.

A logic simulation method for evaluating a logic system including a multi-port memory having a plurality of independently addressable ports, each of which is one of input and output ports, by use of logic simulation, comprising the steps of:

• constructing each of the input and output ports of said multi-port memory in a simulation model form using a corresponding plurality of memory primitives, said constructing step including the steps of:
• (1) setting said plurality of memory primitives representing the input and output ports of said multi-port memory to have a common base address, and
• (2) creating logic primitives for effecting preset logic processes in connection with said respective memory primitives having said common base address by creating one of the logic primitives for transmitting an occurrence of a write operation of a memory primitive representing an input port to a memory primitive representing an output port;
• and
• evaluating the logic system using the constructed simulation model.

A logic simulation apparatus for evaluating a logic system including a multi-port memory having a plurality of independently addressable ports, each of which is one of input and output ports, by use of logic simulation, comprising:

• model creation means for constructing each of the input and output ports of said multi-port memory in a simulation model form using a corresponding plurality of memory primitives, said model creation means including:
• (1) base address setting means for setting said plurality of memory primitives representing the input and output ports of said multi-port memory to have a common base address;
• and
• (2) logic primitive creation means for creating logic primitives for effecting preset logic processes in connection with said respective memory primitives having said common base address, said logic primitive creation means including means for creating one of the logic primitives for transmitting an occurrence of a write operation of a memory primitive representing an input port to a memory primitive representing an output port;
• and
• simulation means for evaluating the logic system using the constructed simulation model.