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AssigneeSilicon Graphics, Inc.
InventorsJohn Brennan, Peter Y. Hsu, William A. Huffman, Paul Rodman, Joseph T. Scanlon, Man K. Tang, Steve J. Ciavaglia
Estimating the term…
A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.
A split level cache memory system in a data processor comprising:
A method for the coherent storage of integer and floating point data used by a split level cache memory system in a data processor, comprising the steps of:
Dependencies are inferred from the claim text.