Digital circuit for the introduction of dither into an analog signal

A dithered analog-to-digital conversion circuit with gain control, comprising:

• an analog to digital converter having an input for receiving an analog video signal, said analog to digital converter converting said analog video signal to an equivalent digital signal having a plurality of digital data samples, each of said digital data samples having thirteen data bits and a sign bit;
• serial to parallel conversion means for receiving said digital equivalent signal and converting said digital equivalent signal from a serial form to a parallel form;
• decoder means for receiving a first logic signal and decoding said first logic signal to provide a second logic signal;
• clock signal generating means for receiving a system clock signal and a frame start signal, said clock signal generating means, responsive to said system clock signal and said frame start signal, generating a strobe data in signal and an internal clock signal;
• a down counter coupled to said decoder means and said clock signal generating means for receiving said internal clock signal and said second logic signal, said down counter, responsive to said internal clock signal, counting down from a first binary number set within said down counter when said down counter receives and decodes said second logic signal;
• said down counter providing a latch pulse when said binary counter counts down a second binary number;
• a Flip-Flop having a data input for receiving a logic one signal, a clock input connected to said down counter for receiving said logic pulse and an output, said Flip-Flop, responsive to said latch pulse, latching to the output of said Flip-Flop said logic one signal;
• gating means having a first input for receiving said logic one signal, a second input for receiving said data strobe in signal, and an output, said logic one signal enabling said AND gate allowing said data strobe in signal to pass through said gating means to provide at the output of said gating means a data strobe out signal;
• a first-in, first-out memory coupled to said serial to parallel conversion means, said clock signal generating means and the output of said gating means, said first-in, first-out memory, responsive to said data strobe in signal, temporarily storing the digital data samples of said digital equivalent signal, said data strobe out signal effecting a retrieval of the digital data samples of said digital equivalent signal stored in said first-in, first-out memory;
• gain control circuit means for receiving a first most significant data bit, a second most significant data bit, a third most significant data bit and a fourth most significant data bit of said digital data samples;
• said gain control circuit means for determining a peak magnitude value of the first, second, third and fourth most significant bits for one digital data sample of a predetermined number of digital data samples;
• said gain control circuit means providing a four bit logic signal, said four bit logic signal being representative of said peak magnitude value of the first, second, third and fourth most significant bits for said one digital data sample;
• said gain control circuit means receiving said latch pulse and being reset by said latch pulse to allow for subsequent determinations of said peak magnitude value;
• a data selector circuit coupled to an output of said first-in, first-out memory for receiving the thirteen data bits of said digital data samples from said first-in, first-out memory;
• said data selector circuit coupled to an output of said gain control circuit means for receiving said four bit logic signal from said gain control circuit means, said data circuit means, responsive to said four bit signal selecting nine data bits of the thirteen data bits of each digital data sample and providing said nine data bits of each digital data sample selected by data selector circuit to an output of said data selector circuit;
• dither generating means for digitally generating a sequence of eight bit dither components;
• binary adder means for combining one of said sequence of eight bit dither components, said nine data bits of each digital data sample and said sign bit for said digital data sample to produce an eight bit digital data output signal;
• and
• a gain encoder circuit coupled to said gain control circuit means for receiving said four bit logic signal;
• said gain encoder circuit encoding said four bit logic signal to provide a three bit logic signal indicative of the nine data bits of each digital data sample selected by said data selector signal.