Algorithmic A/D converter with digitally calibrated output
AssigneeAnalog Devices, Inc.
InventorHae-Seung Lee
Life of this patent
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Abstract
A multistage pipelined algorithmic A/D converter digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. To perform this calibration, measurements are made at the converter to determine the degree of capacitor mismatch for each stage to be calibrated. In the embodiment disclosed, only one stage is calibrated. The remaining stages of the converter are employed to develop the digital calibration data for the stage being measured. This calibration data is stored in a memory forming part of the converter. The stored data is thereafter used during each conversion to cancel the errors due to capacitor mismatch.
Claims18
In an algorithmic A/D converter of the type wherein at least one stage employs a circuit having two capacitors with means for switching said two capacitors successively into different circuit-connection configurations wherein the switching between two such configurations effects a mathematical function, and wherein errors in the converter output will occur if there is mismatch of said two capacitors;
- the method of calibrating said converter to avoid such errors comprising the steps of:
- exercising said one stage by connecting said two capacitors in said circuit successively between a first set of different circuit-connection configurations;
- developing a digital measure of mismatch of said two capacitors from a circuit effect produced by said exercising of said one stage between said first set of circuit-connection configurations;
- storing said digital measure of mismatch in a memory device;
- and
- utilizing said digital measure of mismatch with the digital output of said converter to effect calibration thereof whenever a conversion is performed.
In an algorithmic A/D converter having at least one stage comprising a pair of nominally equal-valued capacitors with means for switching said capacitors successively between different circuit-connection configurations to provide a multiply-by-two mathematical function, and wherein mismatch of said capacitors in such stage can develop errors in the converter output signal;
- said converter further comprising:
- an output register to receive the digital output of the converter;
- memory means forming part of said converter;
- said memory means containing digital calibration data for said at least one stage and representing the degree of said capacitor mismatch;
- and
- means for utilizing the digital calibration data from said memory means with the digital output signal in said output register to provide a calibrated final digital output signal for the converter.
In a multi-stage algorithmic A/D converter of the type wherein at least one stage comprises two capacitors with means for switching said capacitors between different circuit-connection configurations to provide a function, and wherein mismatch of said capacitors in such stage can develop errors in the converter output signal;
- said converter further comprising:
- an output register to receive the digital output of the converter;
- memory means forming part of said converter;
- said memory means containing digital calibration data for said at least one stage and representing the degree of said capacitor mismatch;
- means to exercise said one stage by successively connecting said two capacitors between a first set of different circuit-connection configurations;
- means operable with a second converter stage following said one stage while said one stage is being exercised to develop from said second stage digital calibration data for said memory means;
- and
- means for utilizing the digital calibration data from said memory means with the digital output signal in said output register to provide a calibrated final digital output signal for the converter.
In a multi-stage algorithmic A/D converter of the type wherein at least one stage comprises two capacitors with means for switching said capacitors between different circuit-connection configurations to provide a function, and wherein mismatch of said capacitors in such stage can develop errors in the converter output signal;
- the method of calibrating said one converter stage comprising:
- exercising said one stage by successively connecting said two capacitors between a first set of different circuit-connection configurations;
- while said one stage is being exercised, directing the output of said one stage to the input of a following stage;
- utilizing said following stage to produce a digital measure of the mismatch of said two capacitors;
- and
- in a subsequent operation of said A/D converter, combining said digital measure of mismatch with the output of the converter to provide a calibrated final digital output signal for the converter.
Dependencies are inferred from the claim text.