Bias circuit for providing a stable output current

A bias circuit for supplying a predetermined current to a next-stage circuit, comprising:

• a first node having a first potential;
• a second node having a second potential;
• an output node electrically connected to said next-stage circuit;
• a main bias circuit for supplying said predetermined current from said first node to said output node;
• a third node electrically connected to said output node;
• an auxiliary bias circuit for electrically equalizing the value of current flowing from said first node to said third node with the value of a current flowing from said third node to said second node, the auxiliary bias circuit comprising
• a first MOS transistor having a source electrode electrically connected to said first node and a drain electrode electrically connected to said third node,
• a second MOS transistor having a source electrode electrically connected to said second node and a drain electrode electrically connected to said third node,
• a third MOS transistor having a source electrode electrically connected to said first node,
• a first resistive element having one end electrically connected to a gate electrode of said first MOS transistor and to drain and gate electrodes of said third transistor, and
• a fourth MOS transistor having a source electrode electrically connected to said second node and drain and gate electrodes electrically connected to a gate electrode of said second MOS transistor and to the other end of said first resistive element.

A bias circuit for controlling activation of a next-stage circuit, comprising:

• a first node having a first potential;
• a second node having a second potential;
• an output node electrically connected to said next-stage circuit;
• a main bias circuit comprising a first current mirror circuit,
• the first current mirror circuit comprising a first MOS transistor having a first electrode electrically connected to said first node and second and gate electrodes electrically connected to said output node, and a second MOS transistor having a first electrode electrically connected to said first node, a second electrode electrically connectable to said second node and a gate electrode electrically connected to said output node, the second MOS transistor being activated in response to activation of the first MOS transistor,
• an auxiliary bias circuit comprising second and third current mirror circuits,
• the second current mirror circuit comprising a third MOS transistor having a first electrode electrically connected to said first node, and a fourth MOS transistor having a first electrode electrically connected to said first node with a second electrode electrically connected to said gate electrode of said first MOS transistor and a gate electrode electrically connected to second and gate electrodes of said third MOS transistor, and
• the third current mirror circuit comprising a fifth MOS transistor having a first electrode electrically connected to said second node and second and gate electrodes electrically connected to said second electrode of said third MOS transistor, and a sixth MOS transistor having a first electrode electrically connected to said second node with a second electrode electrically connected to said gate electrode of said first MOS transistor and a gate electrode electrically connected to said gate electrode of said fifth MOS transistor,
• the value of a current flowing in said second current mirror circuit equalizing with the value of a current flowing in said first current mirror circuit.