CMOS programmable resistor-based transconductor

A programmable transconductor for generating a differential current between first and second current output terminals responsive to a differential voltage operably impressed between first and second voltage input terminals, comprising:

• a current source circuit configured to deliver a predetermined mount of current into each of a first summing node and a second summing node;
• a resistor circuit coupled between the first and second summing nodes, the resistor circuit comprising a plurality of individual resistors connected in series and defining a plurality of intermediate nodes between adjacent resistors;
• a first selector circuit for operably coupling a first selected one of the plurality of intermediate nodes to a first feedback node;
• a second selector circuit for operably coupling a second selected one of the plurality of intermediate nodes to a second feedback node;
• a first input circuit, coupled to the first summing node, the first feedback node, and the first voltage input terminal, for operably biasing the first summing node to a suitable voltage to bias the first feedback node to a voltage equal to a voltage operably impressed upon the first voltage input terminal;
• a second input circuit, coupled to the second summing node, the second feedback node, and the second voltage input terminal, for operably biasing the second summing node to a suitable voltage to bias the second feedback node to a voltage equal to a voltage impressed upon the second voltage input terminal;
• thereby operably causing a resistor current to flow through the resistor circuit from the first summing node to the second summing node corresponding to a voltage difference between the first and second selected intermediate nodes divided by a sum of the resistors connected therebetween, resulting in a net current into the first summing node equal to the predetermined amount of current delivered thereinto minus the resistor current, and further resulting in a net current into the second summing node equal to the predetermined amount of current delivered thereinto plus the resistor current;
• wherein the net current into each of the first and second summing nodes is operably coupled to the first and second current output terminals, respectively, thereby resulting in a differential current between the first and second current output terminals corresponding to the differential voltage operably impressed between the first and second voltage input terminals divided by the sum of the resistors coupled between the first and second selected intermediate nodes;
• and
• wherein the first and second selected intermediate nodes are chosen to select a transconductance value from a range of selectable transconductance values.

A variable transconductor for generating a differential current between first and second current output terminals responsive to a differential voltage operably impressed between first and second voltage input terminals, comprising:

• current source means configured to deliver a predetermined mount of current into both a first summing node and into a second summing node;
• programmable resistor means including a string of individual resistors, the string having a first and second plurality of intermediate nodes, coupled between the first and second summing nodes for providing a current path therebetween in accordance with a differential voltage therebetween, and resulting in a net current into the first summing node equal to the predetermined amount of current delivered thereinto plus any current flowing through the resistor means into the first node from the second node, and resulting in a net current into the second summing node equal to the predetermined amount of current delivered thereinto plus any current flowing through the resistor means into the second node from the first node;
• a first transistor configured to operably receive the net current into the first summing node, and for providing this net current to the first current output terminal;
• a second transistor configured to operably receive the net current into the second summing node, and for providing this net current to the second current output terminal;
• a first gain block having a first input coupled to the first voltage input terminal;
• having a second input coupled to one of the first and second plurality of intermediate nodes, and having an output coupled to the control terminal of the first transistor;
• and
• a second gain block having a first input coupled to the second voltage input terminal;
• having a second input coupled to another of the first and second plurality of intermediate nodes, and having an output coupled to the control terminal of the second transistor.