High speed circuit with CMOS and bipolar logic stages

A method of constructing a dedicated logic region of an integrated circuit, said method comprising the steps of:

• providing a bipolar logic stage including
• a common emitter line positioned along an axis, and
• a plurality of bipolar logic blocks arranged along said axis, each of said bipolar logic blocks including a bipolar logic gate with an emitter connected to said common emitter line, each of said bipolar logic blocks further including an emitter-base reverse voltage protection device;
• and
• providing a MOS logic stage including a plurality of MOS logic blocks connected to said plurality of bipolar logic blocks, said MOS logic stage performing logical operations on a set of input signals to generate a set of intermediate signals that are driven by said plurality of bipolar signal drive blocks onto said common emitter line that executes a hardwired logical OR operation on said intermediate signals to produce a high speed output signal.

A method of designing a dedicated logic region of an integrated circuit, said method comprising the steps of:

• specifying a bipolar logic stage with
• a common emitter line positioned along an axis, and
• a plurality of bipolar logic blocks arranged along said axis, each of said bipolar logic blocks including a bipolar logic gate with an emitter connected to said common emitter line, each of said bipolar logic blocks further including an emitter-base reverse voltage protection device;
• and
• establishing a CMOS logic stage including a plurality of CMOS logic blocks connected to said plurality of bipolar logic blocks, said CMOS logic stage performing logical operations on a set of input signals to generate a set of intermediate signals that are driven by said plurality of bipolar signal drive blocks onto said common emitter line that executes a hardwired logical OR operation on said intermediate signals to produce a high speed output signal.