Synchronizer circuit and method for reducing the occurrence of metastability conditions in digital systems

A method of operating a synchronizer circuit coupled between a first digital subsystem operating at a first frequency and a second digital subsystem operating at a second frequency, comprising the steps of either:

• receiving a data signal from the first digital subsystem at an input port of a first synchronizer;
• receiving a clock signal substantially equal to the second clock frequency of the second digital subsystem at a clock port of the first synchronizer;
• and
• activating a first discharge path and a second discharge path coupled to an output node of the first synchronizer in the event the step of receiving the data signal substantially coincides with the step of receiving the clock signal;
• or
• receiving a complementary data signal from the first digital subsystem at a complementary input port of the first synchronizer;
• receiving the clock signal substantially equal to the second clock frequency of the second digital subsystem at a second clock port of the first synchronizer;
• and
• activating a first complementary discharge path and a second complementary discharge path coupled to a complementary output node of the first synchronizer in the event the step of receiving the complementary signal substantially coincides with the step of receiving the clock signal.

A method of providing a synchronizer circuit for use in a digital system for managing data transfer between a first digital subsystem and second digital subsystem operating at different clock frequencies, the synchronizer circuit, comprising the steps of:

• providing an input node coupled to receive an input signal operating at a first frequency;
• providing a signal node configured to generate an output signal at a second frequency;
• providing a discharge node;
• providing a first discharge path coupled between the signal node and the discharge node;
• providing a second discharge path coupled between the signal node and the discharge node;
• and
• a control element coupled to the first discharge path and the second discharge path to selectively discharge the signal node through the first discharge path and the second discharge path to the discharge node in response to the input signal received at the input node, the discharge of the signal node through the first discharge path and the second discharge path helping to reduce the chances of a metastability condition occurring in the synchronizer circuit;
• providing a complementary input node coupled to receive a complementary input signal operating at the first frequency;
• providing a complementary signal node configured to generate a complementary output signal at the second frequency;
• providing a complementary discharge node;
• providing a complementary first discharge path coupled between the complementary signal node and the complementary discharge node;
• providing a complementary second discharge path coupled to between the complementary signal node and the complementary discharge node;
• and
• providing a complementary control element coupled to the complementary first discharge path and the complementary second discharge path to selectively discharge the complementary signal node through the complementary first discharge path and the complementary second discharge path in response to the complementary input signal received at the complementary input node, the discharge of the complementary signal node through the first complementary discharge path and the second complementary discharge path helping to reduce the chances of metastability occurring in the synchronizer circuit.