Reconfigurable programmable interconnect architecture
AssigneeActel Corporation
InventorsAbbas El Gamal, Steve S. S. Chiang
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Abstract
A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open reconfigurable programmable elements situated at the intersection of any two segments to be connected.
Claims14
In an integrated circuit, an electrically programmable interconnect architecture, comprising:
- a plurality of logic modules placed in an array on a substrate, the modules having at least one RAM cell and having connection nodes;
- a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wire segments and wherein at least one of said wire segments is connected to at least one of said connection nodes;
- a plurality of reconfigurable elements, each of said reconfigurable elements having two main terminals, said main terminals connected between selected ones of said wiring segments comprising one of said channels, each of said reconfigurable elements further including a control terminal;
- series-pass transistors connected between selected adjacent ones of said segments, each of said series-pass transistors having a control element, and
- selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.
In an integrated circuit, an electrically programmable interconnect architecture, comprising:
- a plurality of modules placed in an array on a substrate, said modules comprising logic and at least one RAM cell, said plurality of modules further comprising connection nodes;
- a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments in at least one wiring channel is connected to at least one of said connection nodes;
- a plurality of EPROM memory transistors, each of said EPROM memory transistors having a source and a drain, said source and said drain connected between selected ones of said wiring segments comprising one of said wiring channels, said each of EPROM memory transistors further including a control gate;
- configuring circuitry connected to said sources of said EPROM memory transistors, said configuring circuitry selectively rendering said EPROM memory transistors non-conductive.
A user-programmable array logic circuit comprising:
- a plurality of logic modules placed in an array on a substrate, said logic modules comprising at least one RAM cell and having connection nodes;
- a plurality of first wiring channels running in a first direction, said first wiring channels containing a plurality of wiring segments, at least one of said wiring segments connected to at least one of said connection nodes;
- a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, intersecting said first wiring channels at intersections;
- and
- a plurality of EPROM memory transistors each having a source and drain connected between at least one pair of the intersecting wiring channels.
Dependencies are inferred from the claim text.