Insulated gate semiconductor device and method of fabricating

An insulated gate semiconductor device, comprising:

• a semiconductor substrate of a first conductivity type and having a major surface;
• an isolation well of a second conductivity type extending a first distance into the semiconductor substrate;
• a first dopant well of the second conductivity type extending a second distance into the isolation well from the major surface, wherein the second distance is less than the first distance;
• a second dopant well of the first conductivity type inside and extending a third distance into the first dopant well from the major surface, Wherein an interface between the first and second dopant wells forms a P-N junction, and a portion of the first dopant well adjacent a first portion of the major surface and laterally bounded by a portion of the P-N junction and a portion of a boundary between the first dopant well and the isolation well serves as a first channel portion of the insulated gate semiconductor device, the first channel portion having a constant surface doping concentration of a first value, and wherein the first and second conductivity types are different and the third distance is less than the second distance;
• a third dopant well of the first conductivity type extending a fourth distance into the isolation well from the major surface, the third dopant well laterally spaced apart from the first dopant well by a portion of the isolation well adjacent second portion of the major surface and laterally bounded by the third dopant well and the portion of the boundary between the first dopant well and the isolation well, wherein the portion of the isolation well adjacent the second portion of the major surface and laterally bounded by the third dopant well and the portion of the boundary between the first dopant well and the isolation well serves as a second channel portion of the insulated gate semiconductor device, the second channel portion having a constant surface doping concentration of a second value, wherein the second value is less than the first value;
• a gate oxide on at least a portion of the major surface between the second dopant well and the third dopant well;
• a first portion of a gate electrode structure on a first portion of the gate oxide, the first portion of the gate electrode structure being of the first conductivity type;
• a second portion of the gate electrode structure adjacent to and spaced apart from the first portion of the gate electrode structure by a dielectric material, the second portion of the gate electrode structure being of the first conductivity type;
• a third portion of the gate electrode structure adjacent to and spaced apart from another side of the first portion of the gate electrode structure by the dielectric material, the third portion of the gate electrode structure being of the first conductivity type;
• a conductive strap coupling the first, second, and third portions of the gate electrode structure, the conductive strap serving as a gate electrode;
• a first electrode contacting a portion of the second dopant well;
• and
• a second electrode contacting the third dopant well.