Non-volatile semiconductor memory having a ring-shaped floating gate

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate of a first conductive type, the semiconductor substrate having a top surface;
• a memory cell array region provided on the top surface of the semiconductor substrate;
• a plurality of non-volatile memory cells arranged in the memory cell array region;
• and
• word lines and bit lines to provide interconnection between the plurality of non-volatile memory cells, wherein
• each of the plurality of non-volatile memory cells comprises:
• a ring-shaped channel region of the first conductive type embedded in the top surface of the semiconductor substrate;
• a drain region of a second conductive type formed in a zone surrounded by the ring-shaped channel region and embedded in the top surface of the semiconductor substrate;
• a source region of the second conductive type formed outside the ring-shaped channel region and embedded in the top surface of the semiconductor substrate;
• a ring-shaped first gate insulation layer formed on the top surface of the semiconductor substrate in such a manner as to cover the boundary between the ring-shaped channel region and the drain region;
• a ring-shaped floating gate electrode formed on tile ring-shaped first gate insulation layer;
• a second gate insulation layer formed on the surface of the ring-shaped floating gate electrode;
• and
• a control gate electrode which is capacitive-coupled with the ring-shaped floating gate electrode via the second gate insulation layer, and is electrically insulated from the semiconductor substrate, wherein
• at least part of the plurality of non-volatile memory cells share the source region, and
• each of the plurality of word lines includes the control gate electrode in part thereof.