Method of fabricating an asymmetric lightly doped drain transistor device

A method of fabricating an asymmetric lightly doped drain transistor device, comprising the following steps:

• (a) providing a silicon substrate doped with impurities of a first conductivity type and having an active region;
• (b) forming a gate oxide layer on said active region;
• (c) forming a gate structure on said gate oxide layer to form a channel region there beneath in said substrate;
• (d) applying a first ion implantation to implant ions of a second conductivity type into said substrate to form doped source and drain regions at two sides of said channel region;
• (e) forming a barrier layer on said drain region;
• (f) applying a second ion implantation to implant a second conductivity type into said substrate to form a heavily doped first source region, using said barrier layer as a mask;
• (g) applying an oblique angle ion implantation to ions of a first conductivity type into said substrate to form a lightly doped pocket region under said channel region and at side of said heavily doped first source region, using said barrier layer as a mask;
• (h) removing said barrier layer and forming sidewall spacers on side walls of said gate structure;
• and
• (i) applying a third ion implantation to implant ions of a second conductivity type into said substrate to form a heavily doped second source region and a heavily doped drain region, using said sidewall spacers as a mask.