Method for forming a thin film transistor
AssigneeMotorola, Inc.
InventorsBich-Yen Nguyen, Thomas F. McNelly, Philip J. Tobin, James D. Hayden
Life of this patent
Estimating the term…
Abstract
An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
Claims13
A method for forming a thin film transistor comprising the steps of:
- providing a substrate;
- forming a gate electrode overlying the substrate, the gate electrode having a sidewall;
- forming a gate dielectric layer abutting at least a portion of the gate electrode;
- forming a first layer of semiconductive material abutting at least a portion:
- of the gate dielectric layer;
- etching a portion of the first layer of semiconductive material to form an exposed portion of the gate dielectric layer;
- etching the exposed portion of the gate dielectric layer to define a contact opening therein;
- forming a second layer of semiconductive material overlying the first layer of semiconductive material to form a composite layer of semiconductive material overlying the gate dielectric layer, wherein the second layer of semiconductive material also lies within the contact opening;
- patterning the composite layer;
- and
- forming a source region within a first portion of the composite layer and a drain region within a second portion of the composite layer, wherein the source and drain regions define a channel region within a third portion of the composite layer that overlies the gate electrode.
A method for forming a thin film transistor comprising the steps of:
- providing a substrate;
- forming a gate electrode overlying the substrate, the gate electrode having a sidewall;
- forming a gate dielectric layer abutting at least a portion of the gate electrode;
- depositing a first amorphous silicon layer abutting at least a portion of the gate dielectric layer;
- etching a portion of the first amorphous silicon layer to form an exposed portion of the gate dielectric layer;
- etching the exposed portion of 7the gate dielectric layer to define a contact opening therein;
- depositing a second amorphous silicon layer overlying the first amorphous silicon layer to form a composite layer of semiconductive material, wherein the second amorphous silicon layer also lies within the contact opening;
- annealing the composite layer of semiconductive material to recrystallize the first and second amorphous silicon layers;
- patterning the composite layer;
- and
- forming a source region within a first portion of the composite layer and a drain region within second portion of the composite layer, wherein the source region and drain region define a channel region within a third portion of the composite layer that overlies the gate electrode.
Dependencies are inferred from the claim text.