Multi-voltage circuit arrangement and method for accommodating hybrid electronic system requirements

A multi-voltage semiconductor chip, comprising:

• core circuitry having an operating voltage equal to a first voltage level;
• first and second groups of input and output buffer circuits, said first and second groups of input and output buffers coupled to said core circuitry to provide data access between said core circuitry and external devices, each of said input buffers of said first and second groups having an operating voltage equal to said first voltage level;
• first connection means for supplying power, said output buffers of said first group having a power attachment to said first connection means;
• and
• second connection means for supplying power, said output buffers of said second group having a power attachment to said second connection means;
• said output buffers of said first and second groups being operable at said first voltage level and at a second voltage level, respectively, said second voltage level being less than said first voltage level;
• said first and second connection means for supplying power each capable of being user-selectably coupled to one of a first power supply and a second power supply, said second power supply being operative at said second voltage level.

A method of fabricating a multi-voltage semiconductor chip, comprising the steps of:

• selecting a high voltage level and a low voltage level so that the value of said high voltage level is greater than the value of said low voltage level;
• fabricating a core of electronic circuitry to operate at said high voltage level;
• selecting a plurality of regions along the periphery of said core of electronic circuitry;
• and
• disposing a group of I/O circuitry in each of said plurality of regions;
• said step of disposing including the steps of forming input buffers in each of said plurality of regions and providing power to all of said input buffers to operate at said high voltage level;
• said step of disposing including the steps of forming output buffers in each of said plurality of regions, forming a power connection point in each of said plurality of regions and for each of said plurality of regions coupling each of said output buffers within said region to the power connection point corresponding to said region.