Bitline level insensitive sense amplifier

In a memory circuit generating a first signal line and a second signal line, a method for sensing a difference in potential between the first and second signal lines comprising the steps of:

• providing a differential amplifier having a first input and a second input, the first signal line coupled to the first input, the second signal line coupled to the second input, the differential amplifier generating an output having an output potential in response to the first and second signal lines, the differential amplifier having two nodes wherein one of the two nodes is the output, the two nodes coupled to a first potential through a load;
• maintaining the output potential by coupling a first pass device between the output and the first potential, the first pass device directly responsive to the second signal line such that the output potential is maintained by the first pass device in response to the second signal line;
• and
• maintaining a second potential at an other one of the two nodes by coupling a second pass device between the other one of the two nodes and the first potential, the second pass device directly responsive to the first signal line such that the second potential is maintained by the second pass device in response to the first signal line.

A circuit for sensing differential voltage between a first bitline and a second bitline of a memory circuit, the second bitline carrying a complementary signal to first bitline, the circuit comprising:

• a differential amplifier coupled to the first and second bitlines, the differential amplifier generating an output in response to the first and second bitline, the differential amplifier comprising a first transistor and a second transistor, the first transistor responsive to the first bitline, the second transistor responsive to the second bitline, the sources of the first and second transistors coupled together, the output being the drain of the second transistor;
• a load coupled to a first potential and the differential amplifier, the load comprised of a third transistor and a fourth transistor, the gates of the third and fourth transistors coupled together and to the drain of the third transistor, the drain of the third transistor coupled to the drain of the first transistor, the drain of the fourth transistor coupled to the drain of the second transistor, the sources of the third and fourth transistors coupled to the first potential;
• a current source coupled between the differential amplifier and a second potential, the current source comprised of a fifth transistor responsive to an enable signal line;
• an equalization device coupled between the drains of the first and second transistors, the equalization device comprising a sixth transistor responsive to the enable signal line;
• a seventh transistor coupled between the first potential and the drain of the first transistor, the seventh transistor responsive to the second bitline;
• an eight transistor coupled between the first potential and the drain of the second transistor, the eight transistor responsive to the first bitline;
• and
• a ninth transistor coupled between the first potential and the drain of the first transistor, the ninth transistor responsive to the enable signal line.