Integrated circuit chip and pass gate logic family therefor
AssigneeInternational Business Machines Corporation
InventorsDavid P. Appenzeller, Peter Wohl
Life of this patent
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Abstract
An integrated circuit chip with high level logic functions formed from a pass gate logic family. The logic for each logic book includes at least one pass gate. Each book has complementary outputs and a pseudo latch attached to its outputs. If the book is of one FET type, the pseudo latch is of the opposite type. Books are placed in the logic function such that the output pseudo latches redrive opposite logic levels on alternating stages of series-connected books.
Claims23
An integrated circuit chip including at least one high order logic circuit, said at least one high order logic circuit comprising:
- a plurality of logic books;
- each logic book of said plurality of logic books having complementary outputs;
- said plurality of logic books being coupled to perform a predetermined logic function;
- first reinforcing means for reinforcing a first logic level and second reinforcing means for reinforcing a second logic level;
- said plurality of logic books, said first reinforcing means, and said second reinforcing means being coupled appropriately that for any two logic books of said plurality of logic books which are coupled in series, a first logic book of said two logic books cooperates with one reinforcing means of said first reinforcing means and said second reinforcing means to reinforce one logic level of said first logic level and said second logic level, and a second logic book of said two logic books cooperates with the other reinforcing means of said first reinforcing means and said second reinforcing means than said one reinforcing means to reinforce the other logic level of said first logic level and said second logic level than said one logic level;
- and
- each of said first and second reinforcing means including a pseudo latch connected to said complementary outputs.
An integrated circuit including a logic circuit formed from logic books, said circuit comprising:
- a plurality of pass gate logic books each of said pass gate logic books having a complementary pair of outputs;
- said plurality of logic books being of a first type logic book or a second type logic book;
- at least two of said plurality of pass gate logic books being connected in series;
- means for reinforcing a first logic level attached to a first group of said complementary pairs of outputs;
- means for reinforcing a second logic level attached to a second group of said complementary pairs of outputs;
- and,
- said pass gate books being arranged in said logic circuit such that for any two of said plurality of pass gate books being connected in series, the first of said series connected books is of said first type logic book and one logic level is reinforced and the second of said series connected books is of said second type logic book and the other logic level is reinforced.
A logic family for forming multiple stage logic circuits, said logic family comprising:
- a plurality of logic books;
- each logic book of said plurality of logic books having complementary outputs;
- said plurality of logic books being coupled to perform a predetermined logic function;
- first reinforcing means for reinforcing a first logic level and second reinforcing means for reinforcing a second logic level;
- said plurality of logic books, said first reinforcing means, and said second reinforcing means being coupled appropriately that for any two logic books of said plurality of logic books which are coupled in series, a first logic book of said two logic books cooperates with one reinforcing means of said first reinforcing means and said second reinforcing means to reinforce one logic level of said first logic level and said second logic level, and a second logic book of said two logic books cooperates with the other reinforcing means of said first reinforcing means and said second reinforcing means than said one reinforcing means to reinforce the other logic level of said first logic level and said second logic level than said one logic level;
- and
- each of said first and second reinforcing means including a pseudo latch connected to said complementary outputs.
Dependencies are inferred from the claim text.