CMOS clock drivers with inductive coupling
AssigneeTexas Instruments Incorporated
InventorJohn W. Fattaruso
Life of this patent
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Abstract
The invention is a power conserving clock driver circuit operative where a differential pair of clock (clock+ and clock-) signals are desired. The circuit responds to transitions in both clock signals to turn off the clock driver transistors (M1P,M1N) (M2N, M2P) for a period of time. During that period of time, a pass gate configuration (M3N, M3P) is conductive. When this occurs, the charge on one of the capacitive loads C.sub.L1 or C.sub.L2 is transferred through the inductor L.sub.c. In this fashion, part of the charge on one of the capacitive loads is transferred directly to the other capacitive load thereby conserving power. The time period during which this power transfer occurs is the time for one half cycle at the natural resonant frequency of the circuit comprised of L.sub.c, C.sub.L1 and C.sub.L2.
Claims8
A power conserving clock driver circuit comprising,
- a clock for producing a first clock signal and a second clock signal 180.degree. out of phase with said first clock signal;
- a first driver circuit coupled to said first clock signal for producing at a first output a first power clock signal for driving a first capacitive load coupled thereto;
- a second driver circuit coupled to said second clock signal for producing at a second output a second power clock signal for driving a second capacitive load coupled thereto;
- means responsive to the change in level of said first clock signal to make said first driver circuit non-operative during a period of time;
- means responsive to the change in level of said second clock signal to make said second driver circuit non-operative during said period of time;
- and
- means to couple the capacitive load coupled to said first output to the capacitive load coupled to said second output, said means for coupling including an inductor and a switch operative during said period of time to transfer the charge on one said capacitive load through said inductor to the other said capacitive load.
A power conserving clock driver circuit comprising:
- a first terminal for coupling to a first power source;
- a second terminal for coupling to a second power source;
- a first and second P-type transistor coupled to said first terminal;
- a first and second N-type transistor coupled to said second terminal;
- said first P-type transistor and said first N-type transistor being coupled together at a first output terminal;
- said second P-type transistor and said second N-type transistor being coupled together at a second output terminal;
- an inductor with two leads, one lead of which is coupled to one said output terminal;
- and
- a third P-type transistor and a third N-type transistor connected in a pass gate configuration between said other lead of said inductor and said other output terminal.
Dependencies are inferred from the claim text.