Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity
AssigneeFujitsu Limited
InventorEiji Sugiyama
Life of this patent
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Abstract
A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first latch circuit independently of the second latch circuit. This semiconductor integrated circuit device is capable of individually testing the latch circuits of the dual configuration, to ensure the merit of the dual configuration.
Claims14
A semiconductor integrated circuit device comprising:
- a dual configuration latch circuit comprising a first latch circuit and a second latch circuit connected in parallel with each other;
- and
- a macro cell comprising first and second reference voltage generators providing corresponding first and second reference voltages to said first and second latch circuits, respectively.
A semiconductor integrated circuit device comprising:
- first and second latch circuits having a common pair of data input terminals and a common pair of data output terminals and connected in parallel between the common pair of data input terminals and the common pair of data output terminals;
- and
- first and second reference voltage generators respectively outputting first and second reference voltages, wherein said first latch circuit receives the first reference voltage and said second latch circuit receives the second reference voltage.
A semiconductor integrated circuit device comprising:
- first and second reference voltage generators respectively outputting first and second reference voltages, wherein said first latch circuit receives the first reference voltage and said second latch circuit receives the second reference voltage;
- first and second latch circuits having common first and second data input terminals and common sample and hold signal input terminals and common data output signal terminals, wherein:
- the first latch circuit has a third, independent data input terminal;
- the second latch circuit has a fourth, independent data input terminal;
- and
- first, second, third and fourth data signals are received at the first, second, third and fourth data input terminals, and sampling and hold signals are received at the sampling and hold data input terminals.
A semiconductor integrated circuit device comprising:
- an array of cells, each cell comprising first and second latch circuits having a common pair of data input terminals and a common pair of data output terminals and connected in parallel between the common pair of data input terminals and the common pair of data output terminals;
- a plurality of reference voltage generators outputting a plurality of respective output voltages;
- and
- means for connecting first and second reference voltage generators of said plurality of reference voltage generators, respectively outputting first and second reference voltages, to the first and second latch circuits wherein said first latch circuit receives the first reference voltage and the second latch circuit receives the second reference voltage.
Dependencies are inferred from the claim text.