Method of simulating hot carrier deterioration of an MOS transistor

A method of analyzing an integrated circuit of a semiconductor device comprising a plurality of components including an N-MOS transistor, which method comprises:

• operating said semiconductor device;
• predicting deterioration of the N-MOS transistor by simulating hot carrier deterioration;
• and
• taking corrective action in response to simulating hot carrier deterioration by isolating areas of the integrated circuit susceptible to hot carrier degradation effects;
• wherein said simulating hot carrier deterioration of an N-MOS transistor comprises formulas (6) and (7):
• F.sub.N (t)=(W.multidot.B).sup.-n .multidot.I.sub.SUB.sup.mn .multidot.I.sub.D.sup.(1-m)n .multidot.t.sup.n ( 6)
• .DELTA.I.sub.D /I.sub.D =(.DELTA.I.sub.D /I.sub.D).sub.f .multidot.F.sub.N (t) (7)
• where F.sub.N (t) represents a quantity of a hot carrier stress applied until a time t, W represents a width of a gate of said transistor, B represents a coefficient depending on a manufacturing condition of said transistor, I.sub.SUB represents a substrate current, I.sub.D represents a drain current, m represents an index which is deemed to be correlated to impact ionization and generation of interface energy levels, and (.DELTA.I.sub.D /I.sub.D) represents a rate of a variation .DELTA.I.sub.D of said drain current at the time of expiration of a lifetime of said transistor to an initial value of said drain current I.sub.D, wherein
• n is not a constant but is expressed as a function n=g(V.sub.G, V.sub.D) of a gate voltage V.sub.G and a drain voltage V.sub.D which are applied at the time of said hot carrier stress, and said function is determined by a preliminary experiment.