Semiconductor test chip with on wafer switching matrix
AssigneeMitel Corporation
InventorsTajinder Manku, Wenyi Song
Life of this patent
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Abstract
A semiconductor test chip has an array of active semiconductor devices to be individually tested, a number of test lines for connection to external test circuitry, an enabling circuit associated with each device for selectively connecting it to the test lines, an input for receiving an instruction identifying a device that it is desired to test, and a decoder incorporated into the chip for receiving the instruction from the input. The decoder is connected by enabling lines to the individual test devices so that on receipt of an instruction the decoder enables the identified test device such that it becomes connected to the test lines. This circuit is more efficient and less cumbersome than the prior art.
Claims9
A semiconductor test chip comprising:
- a) a matrix of active semiconductor devices that can be individually tested, each active semiconductor device having a plurality n of terminals, where n is an integer greater than 2;
- b) a group of n device measurement lines for connection to external test circuitry, n-1 of said device measurement lines being permanently connected to terminals on said active semiconductor devices, and a remaining one of said device measurement lines being connected to a remaining terminal of each active semiconductor device through switch means associated with each said active semiconductor device;
- c) input means for receiving an instruction identifying a said active semiconductor device that it is desired to test;
- d) decoder means comprising a row decoder and a column decoder incorporated into said chip, said row and column decoders each having enabling lines corresponding to rows and columns of said matrix respectively, and said row and column decoders identifying, in accordance with a said received instruction, a row and column respectively of said active semiconductor device that it is desired to test by activating the corresponding enabling lines thereof;
- and
- e) a logic gate associated with each said active semiconductor device and receiving at its inputs said enabling lines corresponding to the row and column of its active semiconductor device, said logic gate activating the switch means of its associated active semiconductor device in response to enablement of the enabling lines connected to its inputs to connect the remaining terminal of its associated active semiconductor device to the remaining device measurement line and thereby activate said associated active semiconductor device.
Dependencies are inferred from the claim text.