Semiconductor integrated circuit device and a method for manufacturing the same

A semiconductor integrated circuit device having a bipolar transistor and a MOS transistor, comprising:

• a semiconductor body of a first conductivity type;
• a plurality of first regions of a second conductivity type formed at predetermined positions of a surface of said semiconductor body, said first regions having a higher impurity concentration than that of said semiconductor body;
• a plurality of second regions of the second conductivity type formed on said first regions, the impurity concentration of said second regions being gradually decreased from the surface of the second regions toward said semiconductor body;
• a plurality of third regions of the first conductivity type formed on the surface of said semiconductor body, said third regions respectively surrounding the sides of said first regions and having a higher impurity concentration than that of said semiconductor body;
• a vertical bipolar transistor having a collector region formed by one of said plurality of first regions and one of said plurality of second regions;
• and
• a first conductivity type MOS transistor formed in another of said plurality of second regions;
• wherein the impurity concentration of each of said second regions is lower than the impurity concentration of an adjacent first region at a boundary of the first and second regions such that said boundary defines a minimum point of impurity concentration of the combination of the first and second regions, whereby said vertical bipolar transistor can operate at high speed without degrading operating characteristics of said first conductivity type MOS transistor.

A semiconductor integrated circuit device having a bipolar transistor and an MOS transistor, comprising

• a semiconductor body of a first conductivity type;
• a first region of a second conductivity type formed at a predetermined position of a surface of said semiconductor body, said first region having a higher impurity concentration than that of said semiconductor body;
• a second region of the second conductivity type formed on said first region, the impurity concentration of said second region bring gradually decreased from the surface of the second region toward said semiconductor body;
• a third region of the first conductivity type formed on the surface of said semiconductor body, said third region surrounding the sides of said first region and having a higher impurity concentration than that of said semiconductor body;
• a vertical bipolar transistor having a collector region formed by the first region and the second region;
• and
• a first conductivity type MOS transistor formed in said second region;
• wherein the impurity concentration of said second region is lower than the impurity concentration of said first region at a boundary of the first and second regions such that said boundary defines a minimum point of impurity concentration of the combination of the first and second regions, whereby said vertical bipolar transistor can operate at high speed without degrading operating characteristics of said first conductivity type MOS transistor.

A semiconductor integrated circuit device having a bipolar transistor and an MOS transistor, comprising:

• a semiconductor body of a first conductivity type;
• a first region of a second conductivity type formed at a predetermined position of a surface of said semiconductor body, said first region having a higher impurity concentration than that of said semiconductor body;
• a second region of the second conductivity type formed on said first region, the impurity concentration of said second region being gradually decreased from the surface of the second region toward said semiconductor body;
• a third region of the first conductivity type formed on the surface of said semiconductor body, said third region surrounding the sides of said second region and having a higher impurity concentration than that of said semiconductor body;
• a fourth region of the second conductivity type formed at a position of the surface of said semiconductor body spaced from said first region, said fourth region having a higher impurity concentration than that of said semiconductor body;
• a fifth region of the second conductivity type formed in said fourth region, the impurity concentration of said fifth region being gradually decreased from the surface of the fifth region toward said semiconductor body;
• a vertical bipolar transistor having a collector region formed by the first region and the second region;
• and
• a first conductivity type MOS transistor formed in said fifth region,
• wherein the impurity concentration of said second region is lower than the impurity concentration of said first region at a boundary of the first and second regions such that said boundary of said first and second regions defines a minimum point of impurity concentration of the combination of the first and second regions, and wherein the impurity concentration of said fifth region is lower than the impurity concentration of said fourth region at a boundary of the fourth and fifth regions such that the boundary of said fourth and fifth regions defines a minimum point of impurity concentration of the combination of the fourth and fifth regions, whereby said vertical bipolar transistor can operate at high speed without degrading the operating characteristics of said first conductivity type MOS transistor.

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising:

• a semiconductor body of a first conductivity type;
• a first region of a second conductivity type formed at a predetermined position of a surface of said semiconductor body, said first region having a higher impurity concentration than that of said semiconductor body;
• a second region of the second conductivity type formed on said first region, the impurity concentration of said second region being gradually decreased from the surface of the second region toward said semiconductor body;
• a third region of the first conductivity type formed on the surface of said semiconductor body, said third region surrounding the sides of said first region and having a higher impurity concentration than that of said semiconductor body;
• a fourth region of the second conductivity type formed at a position of the surface of said semiconductor body spaced from said first region, said fourth region having a higher impurity concentration than that of said semiconductor body;
• a fifth region of the second conductivity type formed in said fourth region, the impurity concentration of said fifth region being gradually decreased from the surface of the fifth region toward said semiconductor body;
• a vertical bipolar transistor having a collector region formed by the first region and the second region;
• and
• a first conductivity type MOS transistor formed in said fifth region,
• wherein the impurity concentration of said second region is lower than the impurity concentration of said first region at a boundary of the first and second regions such that said boundary of said first and second regions defines a minimum point of impurity concentration of the combination of the first and second regions, and wherein the impurity concentration of said fifth region is lower than the impurity concentration of said fourth region at a boundary of the fourth and fifth regions such that the boundary of said fourth and fifth regions defines a minimum point of impurity concentration of the combination of the fourth and fifth regions, whereby said vertical bipolar transistor can operate at high speed without degrading the operating characteristics of said first conductivity type MOS transistor.

A semiconductor integrated circuit device having a bipolar transistor and an MOS transistor, comprising:

• a semiconductor body having first and second surfaces;
• a first region of a first conductivity type extending from the first surface of said semiconductor body toward the interior of said semiconductor body;
• a plurality of second regions of a second conductivity type extending from the second surface of said semiconductor body toward the interior of said semiconductor body, the impurity concentration of said second regions being gradually decreased with distance from the second surface of said semiconductor body;
• a plurality of third regions of the second conductivity type disposed between said first an second regions within said semiconductor body and in contact with said first and second regions, said third regions having a higher impurity concentration than impurity concentrations of said first and second regions;
• a plurality of fourth regions of the first conductivity type extending from the second surface of said semiconductor body toward the interior of said semiconductor body, said fourth regions being adjacent to the sides of said second and third regions to surround said sides, and said fourth regions being further adjacent to said first region and having a higher impurity concentration than that of said first region;
• a vertical bipolar transistor having a collector region formed by one of said plurality of second regions and one of said plurality of third regions;
• and
• a first conductivity type MOS transistor formed in another of said plurality of second regions,
• wherein the impurity concentration of said second region is lower than the impurity concentration of said third region at a boundary of the second and third regions such that said boundary defines a minimum point of impurity concentration of the combination of the second and third regions, whereby said vertical bipolar transistor can operate at high speed without degrading operating characteristics of said first conductivity type MOS transistor.

A semiconductor integrated circuit device having a bipolar transistor and an MOS transistor comprising:

• a semiconductor body of a first conductivity type,
• a first region of a second conductivity type formed on said semiconductor body,
• a second region of the second conductivity type formed on said semiconductor body and isolated from said first region,
• a vertical type bipolar transistor having a collector region formed of said first region, and
• a MOS transistor of the first conductivity type formed on said second region,
• wherein an impurity concentration profile from the surface of the first region toward said semiconductor body and an impurity concentration profile from the surface of the second region toward said semiconductor body are substantially the same, and further wherein the impurity concentration profile of the first region has a minimum point at a predetermined depth between the surface of said first region and the semiconductor body, and the impurity concentration profile of the second region has a minimum point at substantially the same predetermined depth between the surface of the second region and the semiconductor body.