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US 5,508,547 AGranted
LDMOS transistor with reduced projective area of source region
AssigneeUnited Microelectronics Corp.
InventorSheng-Hsing Yang
Life of this patent
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Abstract
Reduced-size LDMOS transistor having reduced leakage and a reduced propensity to latch-up. The LDMOS transistor has a trench with vertical sidewalls adjacent to a source region to help reduce a vertical projective area of the source region.
Claims3
A semiconductor device comprising:
- (a) a semiconductor substrate of a first conductivity type;
- an insulating material disposed over said substrate to define an active region, a first predetermined location of said active region implanted with impurities of the first conductivity type to form a drain region;
- (c) a gate electrode disposed at a second predetermined location of the active region;
- (d) a trench therein adjacent said gate electrode, said trench having:
- (i) first sidewalls which intersect said substrate essentially normal to a major surface thereof and extend in a direction normal to said major surface for a predetermined distance, and
- (ii) second sidewalls then converging towards each other as the depth of the trench in said substrate increases;
- (e) a first residual region of the substrate, said first residual region being implanted with impurities of the first conductivity type and being disposed immediately adjacent one of the first sidewalls, below and under said gate electrode, without being immediately adjacent said second sidewalls, said first residual region forming a source region;
- and
- (f) a body region implanted with impurities of a second conductivity type material surrounding said trench and said source region.
6 more elements
Dependencies are inferred from the claim text.