Three dimensional FAMOS memory devices
AssigneeTexas Instruments Incorporated
InventorPradeep L. Shah
Life of this patent
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Abstract
Memory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36) are implanted in the semiconductor substrate. Drain regions (38) are also implanted in the column structures (12a, 14a).
Claims20
A plurality of memory cells formed at a semiconductor layer of a first conductivity type, comprising:
- an elongate column structure having a base at a face of the semiconductor layer;
- a plurality of source regions implanted into said face with a dopant to be of a second conductivity type opposite said first conductivity type;
- a plurality of drain regions implanted into said elongate column structure with a dopant to be of a second conductivity type opposite said first conductivity type to define channel areas extending between pairs of said source and drain regions and within said elongate column structure;
- a plurality of floating gates formed insulatively adjacent at least one side of said elongate column structure and insulatively disposed over at least a part of each said channel area;
- and
- a control gate insulatively disposed adjacent at least one of said plurality of floating gates.
A plurality of memory cells formed at a semiconductor layer of a first conductivity type, comprising:
- an elongate column structure having a base at a face of the semiconductor layer and further having sidewalls;
- a plurality Of source regions implanted into said face with a dopant to be of a second conductivity type opposite said first conductivity type;
- a plurality of drain regions implanted into said column structure with a dopant to be of a second conductivity type opposite said first conductivity type to define a channel area extending between each pair of said source and drain regions and within said column structure;
- a plurality of floating gates formed on a portion of said sidewalls of said elongate column structure, each said floating gate insulatively disposed over at least a part of said channel area;
- and
- a control gate insulatively disposed adjacent said floating gate.
A plurality of pairs of memory cells formed at a semiconductor layer of a first conductivity type, comprising:
- an elongate column structure having a base at a face of the semiconductor layer and further having sidewalls:
- a plurality of pairs of source regions implanted into said face on opposite sides of said column structure with a dopant to be of a second conductivity type opposite said first conductivity type;
- a plurality of drain regions implanted into said column structure with a dopant to be of a second conductivity type opposite said first conductivity type to define channel areas extending between said source and drain regions and within said column structure;
- a plurality of pairs of floating gates formed on opposite sides of said column structure on said sidewalls, each of said floating gates insulatively disposed over at least a part of different ones of said channel areas;
- and
- a control gate insulatively disposed adjacent each said floating gate.
An array of memory cells formed at a semiconductor layer of a first conductivity type, said cells formed in rows and columns, comprising:
- a plurality of elongate column structures in rows and columns, each of said elongate column structures having a base at a face of the semiconductor layer;
- for each elongate column structure, a plurality of source regions implanted into said face with a dopant to be of a second conductivity type opposite said first conductivity type;
- for each elongate column structure, a plurality of drain regions implanted into said elongate column structure with a dopant to be of a second conductivity type opposite said first conductivity type to define a channel area extending between all adjacent source region and a said drain region and within said elongate column structure;
- for each channel area, a floating gate formed insulatively disposed over at least a part of said channel area;
- and
- for each floating gate, a control gate insulatively disposed adjacent said floating gate.
An array of memory cells formed at a semiconductor layer of a first conductivity type, said cells formed in rows and columns, comprising:
- a plurality of elongate column structures, each of said elongate column structures having a base at a face of the semiconductor layer and further having sidewalls;
- a plurality of source regions implanted into said face between said elongate column structures with a dopant to be of a second conductivity type opposite said first conductivity type;
- for each column structure, a plurality of drain regions implanted into said column structure with a dopant to be of a second conductivity type opposite said first conductivity type to define channel areas extending between each said source region and a drain region and within said column structure;
- for each said channel area, a plurality of floating gates formed on said sidewalls of said elongate column structures, each of said floating gates insulatively disposed over at least a part of different ones of said channel areas;
- and
- for each floating gate, a control gate insulatively disposed adjacent said floating gate.
Dependencies are inferred from the claim text.