Low voltage memory

A charge storage structure for a memory cell, comprising:

• a current path region for carrying charge carriers of a particular charge carrier type between a source and a drain;
• a floating charge storage region positioned adjacent to said current path region for controlling flow of charge carriers through said current path region in dependence upon charge stored in said floating charge storage region;
• and
• a tunnelling insulator region spacing said floating charge storage region from said current path region by a distance between approximately 5 and 100 angstroms,
• said floating charge storage region having a greater affinity for charge carriers of said particular charge carrier type than said current path region by at least kT, where k is Boltzman's constant and T is a normal operating temperature for said tunnelling insulator in degrees Kelvin.

An FET memory cell, comprising:

• a source region;
• a drain region;
• a channel region between said source region and said drain region,
• said channel region having charge carriers of a particular charge carrier type;
• a control gate region adjacent to said channel region for controlling flow of charge carriers through said channel region;
• a floating gate region between said channel region and said control gate region for charge storage;
• a first insulator region spacing said floating gate region from said control gate region;
• and
• a second insulator region spacing said floating gate region from said channel region by a distance between approximately 5 and 100 angstroms,
• said floating gate region having a greater affinity for charge carriers of said particular charge carrier type than said channel region by at least kT, where k is Boltzman's constant and T is a normal operating temperature for said second insulator region in degrees Kelvin.