Elevated-gate field effect transistor structure and fabrication method

A field effect transistor comprising:

• a compound semiconductor substrate having an active region in a top portion of said substrate;
• an active layer disposed in said active region of said substrate, said active layer having an elevated platform;
• a source region disposed in contact with a first end of said active layer;
• a drain region disposed in contact with a second end of said active layer wherein said elevated platform is higher than said drain region;
• and
• a gate layer disposed directly on said elevated platform wherein said gate layer comprises a refractory metal, said gate layer forms a Schottky junction between said gate layer and said active layer, an edge of said elevated platform is substantially aligned with an edge of said gate layer, and wherein a spacer is disposed adjacent to said gate layer and overlying said active layer.

A field effect transistor comprising:

• a compound semiconductor substrate having an active region in a top portion of said substrate;
• an active layer disposed in said active region of said substrate, said active layer having an elevated platform disposed on an elevated portion of said active layer wherein an upper surface of said active layer is in a position higher than said drain region and lower than said elevated platform;
• a source region disposed in contact with a first end of said active layer;
• a drain region disposed in contact with a second end of said active layer wherein said elevated platform is higher than said drain region and said drain region is disposed apart from said elevated portion;
• and
• a gate layer disposed directly on said elevated platform wherein said gate layer forms a Schottky junction between said gate layer and said active layer.

A metal semiconductor field effect transistor comprising:

• a compound semiconductor substrate having a field oxide layer disposed thereon that defines an active region in a surface portion of said substrate;
• an active layer disposed in said active region, wherein said active layer has an elevated platform;
• a refractory metal gate layer formed directly on said elevated platform, wherein an edge of said elevated platform is substantially aligned with an edge of said gate layer;
• and
• source and drain regions disposed in said active region on opposite sides of said gate layer, wherein said elevated platform is higher than said source region and higher than said drain region.

A metal semiconductor field effect transistor comprising:

• a compound semiconductor substrate having a field oxide layer disposed thereon that defines an active region in a surface portion of said substrate;
• an active layer disposed in said active region, wherein said active layer has an elevated platform and has an upper surface in a position higher than said drain region and lower than said elevated platform;
• a refractory metal gate layer formed directly on said elevated platform;
• and
• source and drain regions disposed in said active region on opposite sides of said gate layer, wherein said elevated platform is higher than said source region and higher than said drain region.