Single-chip GPS receiver digital signal processing and microcomputer
AssigneeTrimble Navigation Limited
InventorsChung Y. Lau, Kreg A. Martin, Gary W. Lake
Life of this patent
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Abstract
An embodiment of the present invention combines, on a single integrated circuit, an eight channel GPS receiver, a 68330-type microprocessor, a 68681-type DUART serial communications controller, an analog-to-digital converter, a real-time clock, a random access memory and a boot read-only memory. A system integration module and inter-module bus allow tri-state control of the microprocessor such that a commercially available 68332-type emulator may be used for software development.
Claims11
A digital integrated circuit (IC) for providing digital processing in a global positioning system (GPS) navigation environment, the IC comprising:
- a single semiconductor substrate providing for connection to a single power supply voltage;
- a microcomputer (CPU) having address and data bus connections to a random access memory (RAM) and a boot-up read only memory (ROM), said microcomputer, said RAM, said ROM, and all of said bus connections being integrated on said substrate and providing acquisition and tracking of navigation satellite transmissions;
- a multi-channel GPS receiver including a digital signal processing unit connected to support said acquisition and tracking by the microcomputer and providing satellite navigation including code correlation, position and velocity calculation, said multi-channel GPS receiver being integrated on said substrate;
- and
- a peripheral interface providing connection of an analog-to-digital converter (ADC) and a dual universal asynchronous receiver/transmitter (DUART) to the CPU, said peripheral interface, said ADC, and said DUART being integrated on said substrate.
An integrated circuit (IC) with a digital signal processor (DSP) for determining a position and velocity of a satellite navigation receiver from radio signals transmitted by orbiting navigation satellites, the DSP comprising:
- a single semiconductor chip having a plurality of input/output (I/O) pins for external connections;
- a set of IC pin multiplexers fully disposed on the chip and connected to said I/O pins;
- a dual universal asynchronous receiver transmitter (DUART) connected to the set of IC pin multiplexers for serial data communications and fully disposed on the chip;
- a read only memory (ROM) comprising a boot code program for selecting an external memory having a custom initialization code and fully disposed on the chip;
- a random access memory (RAM) mapped in a memory space adjacent to the ROM and fully disposed on the chip;
- a microcomputer (CPU) connected to the ROM and the RAM and providing support for GPS navigation digital processing, GPS code correlation and position and velocity calculation, user keyboard and display interfacing, and general input/output functions, and fully disposed on the chip;
- a plurality of GPS receiver channels connected to the set of IC pin multiplexers and the CPU for demodulating navigation satellite carrier signals simultaneously received from a plurality of orbiting GPS satellites, and fully disposed on the chip;
- and
- a global channel controller connected to the set of IC pin multiplexers and having a sample circuit connected for intermediate frequency (IF) demodulation, a process interrupt circuit connected to the CPU, a millisecond event counter connected to the CPU, an interrupt generator connected to the CPU, a real time clock (RTC) connected to the CPU, an IF input selector connected to the set of IC pin multiplexers, and a channel controller connected to the plurality of GPS receiver channels, and fully disposed on the chip.
Dependencies are inferred from the claim text.