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US 5,504,444 AGranted
Driver circuits with extended voltage range
AssigneeArithmos, Inc.
InventorCharles F. Neugebauer
Life of this patent
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Abstract
Novel high voltage amplifiers that are capable of being monolithically integrated using low voltage semiconductor fabrication processes are described and claimed. A cascade of low voltage current mirrors is described that can act as a high voltage amplifier output circuit. A high voltage current source circuit also is described and is constructed from the series combination of a low voltage transistor and a parasitic field oxide transistor. Additionally, a differential amplifier having bias current shunting transistors is described that can be used to limit quiescent current from the power supply of the high voltage amplifiers.
Claims37
An apparatus for displaying video image information on a liquid crystal display, comprising:
- (a) a cascade of at least two well current mirrors having at least a first and last current mirror, wherein each current mirror of the cascade has an output current terminal, an upper rail terminal and at least one input current terminal;
- (b) means for connecting the output current terminal of each respective well current mirror in the cascade, except for the last well current mirror in the cascade, to the upper rail terminal of the well current mirror immediately following in the cascade;
- (c) an output power source with at least a first and second terminal;
- (d) means for connecting the upper rail of the first well current mirror in the cascade to the first terminal of the output power source;
- (e) means for connecting the output current terminal of the last well current mirror in the cascade to the second terminal of the output power source;
- (f) a plurality of driving electrodes for activating the liquid crystal display to display an image;
- (g) means for connecting at least one of the driving electrodes of the liquid crystal display to the upper rail terminal of one of the well current mirrors in the cascade;
- (h) current source means for generating a current, wherein the current source means is connected to the respective input current terminals of the well current mirrors in the cascade;
- and
- (i) means for controlling the current source means with control signals representative of the video image information.
7 more elements
An apparatus for generating an output signal on an output electrode, comprising:
- (a) a first set of current sources;
- and
- (b) a first cascade of current mirrors having at least a first and second current mirror, wherein the second current mirror may be the last current mirror in the first cascade, each current mirror having an upper rail terminal, at least one input current terminal and an output current terminal, wherein the current sources are connected to the well current mirrors in the first cascade, the upper rail terminal of the first current mirror of the first cascade is connected to a first terminal of an output power supply and the output current terminal of each current mirror other than the last current mirror in the first cascade is connected to the upper rail terminal of the immediately following current mirror and wherein
- the output current terminal of the last current mirror in the first cascade of current mirrors is connected to the output electrode.
1 more element
A circuit for driving a liquid crystal display, comprising:
- (a) a bias current generating circuit;
- (b) a differential pair of transistors, wherein the differential pair of transistors is connected to the bias current generating circuit;
- (c) bias current shunting means for limiting quiescent current from an output power supply, wherein the bias current shunting means is also connected to the bias current generating circuit;
- and
- (d) an output stage, wherein the output stage is connected to the differential pair of transistors and to the liquid crystal display and generates an output signal in response to signals generated by the differential pair of transistors.
2 more elements
A circuit for generating an output voltage in response to an input voltage, comprising:
- (a) a cascade of at least two well current mirrors having at least a first and last current mirror, wherein each current mirror of the cascade has an output current terminal, an upper rail terminal and at least one input current terminal, and wherein the output current terminal of each respective well current mirror in the cascade, except for the last well current mirror in the cascade, is electronically connected to the upper rail terminal of the well current mirror immediately following in the cascade;
- (b) an output power supply comprising at least a first and second terminal, wherein the upper rail of the first well current mirror in the cascade is electronically connected to the first terminal of the output power supply and wherein the output current terminal of the last well current mirror in the cascade is electronically connected to the second terminal of the output power supply;
- and
- (c) at least one current source, wherein the current source is connected to the respective input current terminals of the well current mirrors in the cascade and wherein the current source is controlled by control signals representative of the input voltage.
1 more element
A circuit for processing input signals into output signals, comprising:
- (a) a bias-current source;
- (b) a differential pair of transistors, wherein each differential pair transistor has a gate, drain and source, wherein the input signals are applied to the gates of the differential pair transistors, and wherein the source of each differential pair transistor is electrically connected to the bias-current source;
- (c) bias-current shunting transistors, wherein the bias-current shunting transistors are electrically connected to the bias-current source;
- (d) an output stage, wherein the output stage is electrically connected to the drain of each differential pair transistor and to an output power supply, and whereby the bias-current shunting transistors limit quiescent current from the output power supply.
1 more element
Dependencies are inferred from the claim text.