Integrated multichip memory module structure

An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising:

• a memory subunit having N memory chips (wherein N.gtoreq.2), each memory chip of the memory subunit having M memory devices (wherein M.gtoreq.2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure;
• and
• logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N.times.M memory devices exists which appears to said external circuitry to comprise said single chip memory structure with N.times.M memory devices;
• and
• wherein the logic means comprises at least two logic chips mechanically coupled to the memory subunit.

An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising:

• a memory subunit having N memory chips (wherein N.gtoreq.2), each memory chip of the memory subunit having M memory devices (wherein M.gtoreq.2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure;
• and
• logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N.times.M memory devices exists which appears to said external circuitry to comprise said single chip memory structure with N.times.M memory devices;
• and
• wherein the logic means includes non-semiconductor type devices coupled to said memory subunit.

A multichip integrated circuit package comprising:

• a plurality of semiconductor chips of similar dimensions coupled together in a stack having an end surface and at least one side surface;
• a lead frame secured to the stack at its end surface, said lead frame having an inner opening extending therethrough such that a portion of the stack's end surface remains exposed;
• a semiconductor chip of smaller dimensions than the similar dimensions of the plurality of semiconductor chips forming the stack, the semiconductor chip of smaller dimensions residing within the inner opening of the lead frame and being secured to the portion of the stack's end surface remaining exposed;
• and
• metallurgy means for electrically interconnecting the plurality of semiconductor chips forming the stack, the semiconductor chip of smaller dimensions and the lead frame such that a dense multichip integrated circuit package is defined from semiconductor chips having different dimensions.

An integrated multichip memory module comprising:

• N memory chips (wherein N.gtoreq.2) each having M memory devices (wherein M.gtoreq.2), each memory chip also having two substantially parallel planar main surfaces and an edge surface, said N memory chips being stacked together to form a subunit having at least one side surface and an end surface, the at least one side surface of the subunit being defined by the edge surfaces of the N memory chips, and the end surface of the subunit extending parallel to the planar main surfaces of the N memory chips forming the subunit, at least some of said N memory chips including transfer metallurgy extending to the at least one side surface of the subunit;
• a first metallization pattern disposed on said subunit's at least one side surface and electrically connecting with the transfer metallurgy extending to the at least one side surface of the subunit;
• an electrical interface layer disposed adjacent to the end surface of the subunit, said electrical interface layer having two substantially parallel planar main surfaces and an edge surface, one of said substantially parallel planar main surfaces of said electrical interface layer being coupled to the end surface of the subunit, the edge surface of the electrical interface layer aligning with the at least one side surface of said subunit, said electrical interface layer having a second metallization pattern disposed therethrough, said second metallization pattern electrically connecting with said first metallization pattern on the at least one side surface of the subunit;
• and
• a logic chip mechanically coupled to an exposed planar main surface of the electrical interface layer and electrically connected to said second metallization pattern such that said logic chip is electrically connected to the memory chips having said transfer metallurgy extending to the at least one side surface of the subunit through said first and second metallization patterns, said logic chip including means for coordinating external communication with said N memory chips of said subunit.