Multiplication circuit having rounding function

Abstract

A product P is calculated by multiplying a multiplicand X and a multiplier factor Y which are 16-bit fixed-point numbers and binary numbers in two's complement notation. Thus obtained product P is 31-bit length and the most significant bit thereof is a sign bit. Further, the product P is rounded down or rounded off to obtain a 16-bit rounded result PR. At this time, the 15-bit rounding data R to be added to the product P is changed according to the sign of the product P which is predicted so as to obtain respective rounded results which have the same absolute value from the two products which have different signs from each other and the same absolute value. In detail, in a case of rounding-down, "0000" and "TFFF" (both in hexadecimal numeral) are respectively generated as the rounding data when the product P is positive and when the product P is negative. In a case of rounding-off, "4000" and "3FFF" (both in hexadecimal numeral) are respectively generated as the rounding data R when the product P is positive and when the product P is negative. The rounding data is added to the less significant 15 bits of the thus calculated product P and the less significant 15 bits of the thus added result are deleted to make the remaining 16 bits the rounded product PR.

Dependencies are inferred from the claim text.