Method for accessing and transmitting data to/from a memory in packets
AssigneeRambus Inc.
InventorsMichael Farmwald, Mark Horowitz
Life of this patent
Estimating the term…
Abstract
A method of transmitting digital information to a memory circuit of a plurality of memory circuits of a computer system through a multiline bus of the computer system is described. The plurality of memory circuits are coupled together via the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. A first word of a packet is transmitted onto the multiline bus. A second word of the packet is then transmitted onto the multiline bus. The second word of the packet includes a first portion of an address. A third word of the packet is transmitted onto the multiline bus. The third word of the packet includes a second portion of the address.
Claims6
A method of addressing a first memory among a plurality of memories coupled to a bi-directional multiline bus for a memory operation from a master also coupled to the bus, comprising the steps of:
- (A) transmitting from the master a first word of a packet to the bus, wherein the bus (1) does not include separate device selection lines for the memories and (2) has a total number of lines less than a total number of bits in any single address, wherein the first word includes (1) a device ID of the first memory and (2) a first portion of an address that alone cannot address any memory location within each of the memories;
- (B) receiving the first word in the first memory from the bus, wherein the first memory is enabled to receive subsequent words of the packet after receiving the device ID in the first word from the bus;
- (C) transmitting from the master a second word of the packet to the first memory via the bus, wherein the second word includes a second portion of the address such that the first memory is selected and addressed for the memory operation without a separate device selection line:
- (D) combining the first and second portions of the address together in the first memory to form the address for addressing a location within the first memory;
- (E) Reading/Writing the location within the first memory using the combined address.
Dependencies are inferred from the claim text.