Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device

An input output control unit that connects a host processor to an external input/output bus that is connected to at least one external master device, the input output control unit and the host processor are also connected to a memory device via a memory control unit, the input output control unit comprising:

• a first dedicated path for the transfer of data read from the at least one external master device or data written from the at least one external master device to the memory control unit, or for the transfer of data returned from a read of the memory device from the memory control unit to the at least one external master device;
• a second dedicated path for transfer of data written by the host processor from the memory unit to the at least one external master device;
• a third dedicated path, connected between the memory control unit and the at least one external master device for transfer of memory addresses for identification of addressed memory segments;
• and
• interface logic, to permit data of differing widths to be transferred between the memory control unit and the at least one external master device;
• wherein the input output control unit is configured to provide status information to the host processor, and the input output control unit and the host processor are located on a single chip.

A microprocessor system comprising:

• a memory control unit;
• a memory unit connected to said memory control unit via a first bus;
• a host processor connected to said memory control unit via a cache control unit, wherein said host processor is configured to execute software instructions stored at memory locations within said memory unit and said cache control unit operates as a buffer for storing said software instructions;
• an input output control unit connected to said memory control unit via a second bus and connected to at least one peripheral device via a third bus, wherein said input output control unit is configured to provide status information for said host processor, said input output control unit comprising,
• a first dedicated path for the transfer of data read from the at least one peripheral device or data written from said at least one peripheral device to said memory control unit, or for the transfer of data returned from a read of the memory .unit from said memory control unit to said at least one peripheral device when said at least one peripheral device is operating as a master device;
• a second dedicated path for transfer of data written by the host processor from said memory control unit to said at least one peripheral device;
• and
• a third dedicated path, connected between said second bus and said third bus, for transfer of memory addresses for identification of addressed memory segments.

A microprocessor system comprising:

• a memory control unit;
• a memory unit connected to said memory control unit via a first bus;
• a host processor connected to said memory control unit via a cache control unit, wherein said host processor is configured to execute software instructions stored at memory locations within said memory unit and said cache control unit operates as a buffer for storing said software instructions;
• an input output control unit connected to said memory control unit via a second bus and connected to at least one peripheral device via a third bus, wherein said input output control unit is configured to provide status information for said host processor, said input output control unit comprising,
• a first dedicated path for the transfer of data read from the at least one peripheral device or data written from said at least one peripheral device to said memory control unit, or for the transfer of data returned from a read of the memory unit from said memory control unit to said at least one peripheral device when said at least one peripheral device is operating as a master device:
• a second dedicated path for transfer of data written by the host processor from said memory control unit to said at least one peripheral device, wherein said second dedicated path comprises a write data queue that is a first-in-first-out buffer;
• and
• a third dedicated path, connected between said second bus and said third bus, for transfer of memory addresses for identification of addressed memory segments.

A microprocessor system comprising:

• a memory control unit;
• a memory unit connected to said memory control unit via a first bus;
• a host processor connected to said memory control unit via a cache control unit, wherein said host processor is configured to execute software instructions stored at memory locations within said memory unit and said cache control unit operates as a buffer for storing said software instructions;
• an input output control unit connected to said memory control unit via a second bus and connected to at least one peripheral device via a third bus, wherein said input output control unit is configured to provide status information for said host processor, said input output control unit comprising,
• a first dedicated path for the transfer of data read from the at least one peripheral device or data written from said at least one peripheral device to said memory control unit, or for the transfer of data returned from a read of the memory unit from said memory control unit to said at least one peripheral device when said at least one peripheral device is operating as a master device;
• a second dedicated path for transfer of data written by the host processor from said memory control unit to said at least one peripheral device;
• and
• a third dedicated path, connected between said second bus and said third bus, for transfer of memory addresses for identification of addressed memory segments, wherein said third dedicated path comprises:
• (a) a request queue, coupled to said memory control unit via said second bus, to store read or write request information from said host processor;
• (b) an address sequence generator, coupled to said request queue, to generate a continuous sequence of addresses from said read or write request information;
• (c) a request buffer, coupled to said memory control unit via said second bus, to buffer read request information from said at least one peripheral device;
• and
• (d) a comparator, coupled to said request buffer, configured to check whether a data block transferred from said at least one peripheral device has an address that falls within an address range associated with a requested data block, and further configured to determine whether a first address associated with an external read from said at least one peripheral is contiguous with a second address associated with said external read.

A microprocessor system comprising:

• a memory control unit;
• a memory unit connected to said memory control unit via a first bus;
• a host processor connected to said memory control unit via a cache control unit, wherein said host processor is configured to execute software instructions stored at memory locations within said memory unit and said cache control unit operates as a buffer for storing said software instructions;
• an input output control unit connected to said memory control unit via a second bus and connected to at least one peripheral device via a third bus, wherein said input output control unit is configured to provide status information for said host processor, said input output control unit comprising,
• a first dedicated path for the transfer of data read from the at least one peripheral device or data written from said at least one peripheral device to said memory control unit, or for the transfer of data returned from a read of the memory unit from said memory control unit to said at least one peripheral device when said at least one peripheral device is operating as a master device, wherein said first dedicated path comprises a read/write data array, coupled to said second bus, to temporarily store data being transferred between said memory control unit and said at least one peripheral device in response to an external read operation, wherein said external read operation requests larger blocks of data than required by said at least one peripheral device;
• a second dedicated path for transfer of data written by the host processor from said memory control unit to said at least one peripheral device;
• and
• a third dedicated path, connected between said second bus and said third bus, for transfer of memory addresses for identification of addressed memory segments.

A microprocessor system comprising:

• a memory control unit;
• a memory unit connected to said memory control unit via a first bus;
• a host processor connected to said memory control unit via a cache control unit, wherein said host processor is configured to execute software instructions stored at memory locations within said memory unit and said cache control unit operates as a buffer for storing said software instructions;
• an input output control unit connected to said memory control unit via a second bus and connected to at least one peripheral device via a third bus, wherein said input output control unit is configured to provide status information for said host processor, said input output control unit comprising,
• a first dedicated path for the transfer of data read from the at least one peripheral device or data written from said at least one peripheral device to said memory control unit, or for the transfer of data returned from a read of the memory unit from said memory control unit to said at least one peripheral device when said at least one peripheral device is operating as a master device;
• a second dedicated path for transfer of data written by the host processor from said memory control unit to said at least one peripheral device;
• a third dedicated path, connected between said second bus and said third bus, for transfer of memory addresses for identification of addressed memory segments;
• an on-chip video processor and a universal asynchronous receiver/transmitter both connected to said third bus;
• and
• an on-chip request buffer, coupled to said video processor, configured to store write or read request information, whereby said video processor does not have to arbitrate for said third bus before making write or read requests.

A microprocessor system comprising:

• a memory control unit;
• a memory unit connected to said memory control unit via a first bus;
• a host processor connected to said memory control unit via a cache control unit, wherein said host processor is configured to execute software instructions stored at memory locations within said memory unit and said cache control unit operates as a buffer for storing said software instructions;
• an input output control unit connected to said memory control unit via a second bus and connected to at least one peripheral device via a third bus, wherein said input output control unit is configured to provide status information for said host processor, said input output control unit comprising,
• a first dedicated path for the transfer of data read from the at least one peripheral device or data written from said at least one peripheral device to said memory control unit, or for the transfer of data returned from a read of the memory unit from said memory control unit to said at least one peripheral device when said at least one peripheral device is operating as a master device wherein said first dedicated path comprises a read/write (R/W) data array, wherein said R/W data array operates as a cacheable RAM during external reads from said at least one peripheral device, and as a first-in-first-out buffer during reads internal to said input output control unit and during external writes to said host processor;
• a second dedicated path for transfer of data written by the host processor from said memory control unit to said at least one peripheral device;
• and
• a third dedicated path, connected between said second bus and said third bus, for transfer of memory addresses for identification of addressed memory segments.