Electronic apparatus with interchangeable peripheral device and a processor interrupt feature

An electronic apparatus provided with an interchangeable peripheral device detachably connected to a CPU, comprising:

• a bus line connected to said CPU, said peripheral device being detachably connected to said bus line;
• means for detecting a connection of said peripheral device to said bus line before said peripheral device comes into contact with a connector of said CPU;
• means for generating a detection signal of said detecting means;
• means coupled to said CPU for outputting a halt control signal;
• means coupled to said CPU for outputting an interruption control signal;
• means for controlling said means for outputting a halt control signal in such a manner that when said CPU is in normal operation, said control means inhibits said output means from outputting the halt control signal, when a halt preprocess is completed and the generation of said detection signal is confirmed, said control means enables said output means to output the halt control signal, and after completion of the halt preprocess, said control means inhibits said output means from outputting the halt control signal;
• and
• means for controlling said means for outputting the interruption control signal in such a manner that when said CPU is in normal operation, said control means enables said output means to output the interruption control signal, when said detection signal is generated and the halt preprocess is executed, said control means inhibits said output means from outputting the interruption control signal, and further after it is confirmed that the detection signal is not generated, said control means enables said output means to output the interruption control signal.