Feedback register configuration for a synchronous vector processor employing delayed and non-delayed algorithms

A processing system for receiving input data as parallel data words which are received at periodic time intervals, processing the received input data at said periodic time intervals in processing cycles and outputting processed data for each processing cycle, comprising:

• a data input register for receiving and storing the input parallel data words in a serial manner;
• a plurality of processor elements for receiving stored data from said data input register, each for processing one of said parallel data words and outputting said processed data during a given processing cycle in accordance with at least two predetermined processing algorithms, which predetermined processing algorithms have associated therewith variables that are utilized by each of said processor elements during processing, said predetermined algorithms comprising a delayed algorithm and a non-delayed algorithm;
• a data output register for receiving said processed data from said plurality of processor elements and storing said processed data, and subsequently outputting said processed data therefrom;
• an auxiliary register for storing select portions of said processed data received by said data output register;
• a feedback circuit for selectively inputting the contents of said auxiliary register to said plurality of processing elements as one of said variables;
• and
• a controller for controlling the operation of said processing elements to process said received data to calculate a predetermined variable in one of said processing cycles utilizing data received from said data input register and transferring said calculated predetermined variable to said data output register and to said auxiliary register, and, during a processing cycle subsequent to a current processing cycle, utilizing said calculated predetermined variables stored in said auxiliary register for processing of data by said processing elements, said delayed algorithm utilizing said calculated predetermined variable stored in said auxiliary register, said controller comprising:
• a current controller for processing data received in said one processing cycle by said non-delayed algorithm to calculate said variable for storage in said auxiliary register;
• a delay device for storing data received in said one processing cycle for use in a cycle subsequent to said one processing cycle that occurs n processing cycles later;
• a delay controller for processing said delayed data delayed by said delay device in said one processing cycle by said delayed algorithm and utilizing said calculated predetermined variable calculated during a processing cycle that occurred by n previous processing cycles;
• and
• said variable calculated in said one processing cycle utilized in said processing cycle subsequent to said one processing cycle by said delay controller.