Prefetching into a cache to minimize main memory access time and cache size in a computer system

A computer system, comprising:

• (A) a processor;
• (B) a main memory;
• (C) a cache subsystem coupled to the processor and the main memory, wherein the cache subsystem further comprises
• (i) a prefetch buffer coupled to the processor and the main memory, wherein the prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor, wherein the predicted address is based upon a last memory fetch from the processor;
• (ii) a main cache coupled to the processor and the main memory, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer, wherein the main cache stores a second data fetched from the main memory in accordance with an address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address, wherein the address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.

A memory access method in a cache subsystem coupled to a process and a main memory in a computer system, comprising the steps of:

• (A) receiving an address for a memory fetch from the processor;
• (B) determining if the address is an unpredictable address by determining if the address is contained in the cache subsystem, wherein the address is an unpredictable address if the cache subsystem does not contain the address;
• (C) if the address is an unpredictable address, then fetching a first data from the main memory into a main cache of the cache subsystem in accordance with the unpredictable address, wherein the main cache only stores data fetched by unpredictable addresses;
• (D) generating a predicted address for a next memory fetch by the processor based upon the unpredictable address and prefetching a second data from the main memory from the predicted address and then storing the second data in a prefetch buffer, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer.