US 5,499,352 A · Floating point register alias table FXCH and retirement floating point register array

Abstract

A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found. An efficient FXCH operation is implemented within the floating point RAT mechanism by switching 6-bit physical register pointers rather than switching the actual data for each physical register which is 86-bits wide. There is a retirement floating point RAT array with dual valid bits and a dual TOS pointer to account for speculative FXCH operations in addition to another floating point RAT array. The retirement floating point RAT array is updated only upon uop retirement whereas the floating point RAT array is updated at uop issuance.

Claims51

Dependent claims

An apparatus for renaming a current set of logical registers associated with a current set of operations, said apparatus comprising:

a retirement register file means for maintaining register values associated with non-speculative operations;
array means for renaming said logical registers of said current set of logical registers to physical registers, said physical registers residing within a separate array means, said array means comprising a plurality of addressable entries corresponding to individual logical registers, said plurality of addressable entries for storing pointers to individual physical registers;
and
retirement array means for maintaining a retirement register ordering of registers within said retirement register file means, said retirement array means comprising a plurality of addressable entries for storing pointers to individual registers of said registers of said retirement register file means;
means for updating said array means based on issuing operations of said current set of operations which are speculative;
and
means for updating said retirement array means based on retiring operations which are non-speculative.

4 more elements

An apparatus for renaming a current set of logical registers associated with a current set of operations for eliminating false data dependencies between said operations, said apparatus comprising:

a retirement register file means for maintaining register values associated with retired operations;
array means for renaming said logical registers to physical registers, said array means comprising:
a plurality of addressable entries corresponding to said logical registers for storing pointers to said physical registers;
and stack valid bit means for indicating if valid data is pointed to by said addressable entries of said array means;
and
retirement array means for maintaining a retirement register ordering of said retirement register file means, said retirement array means comprising:
a plurality of addressable entries for storing pointers to said retirement register file means;
and retirement stack valid bit means for indicating if valid data is pointed to by said addressable entries of said retirement array means.

5 more elements

An apparatus for renaming a current set of logical registers to physical registers, said current set of logical registers associated with a current set of operations, wherein said logical registers and said physical registers are stack based, said apparatus comprising:

a retirement register file for maintaining register values of retired operations;
an array for renaming said logical registers to said physical registers, said array comprising:
a plurality of addressable entries corresponding to said logical registers;
and a top of stack pointer for indicating a current top of stack entry of said plurality of addressable entries of said array;
retirement array for maintaining a retirement register ordering of said retirement register file, said retirement array comprising:
a plurality of addressable entries for storing pointers to said retirement register file;
and retirement top of stack pointer for indicating a current top of stack entry of said plurality of addressable entries of said retirement array;
logic for updating said array upon issuance of individual operations of said current set of operations;
and
logic for updating said retirement array upon retirement of individual operations.

7 more elements

In a microprocessor, an apparatus for processing an exchange operation between a first logical register and a second logical register, said apparatus comprising:

a retirement register file means for maintaining register values stored by nonspeculative operations;
array means for renaming said logical registers of said current set to physical registers, said array means comprising a plurality of addressable entries corresponding to individual logical registers, said plurality of addressable entries for storing pointers to individual physical registers;
retirement array means for maintaining a retirement register ordering of registers within said retirement register file means, said retirement array means comprising a plurality of addressable entries for storing pointers to individual registers of said retirement register file means;
first swapping means for swapping pointers associated with two addressable entries of said array means corresponding to said first logical register and said second logical register of said exchange operation when said exchange operation is issued and speculative;
and
second swapping means for swapping pointers associated with two addressable entries of said retirement array means corresponding to said first logical register and said second logical register of said exchange operation when said exchange operation is retired and non-speculative.

3 more elements

A method of renaming a current set of logical registers to physical registers, said logical registers associated with a current set of operations, said method comprising the steps of:

providing a retirement register file for maintaining register values stored by nonspeculative operations;
renaming said logical registers to said physical registers upon issuance of said current set of operations, said step of renaming comprising the step of storing pointers to said physical registers into addressable entries of an array corresponding to said logical registers;
and
updating a retirement register ordering of registers within said retirement register file upon retirement of individual operations, said step of updating said retirement register ordering comprising the step of storing pointers to said registers of said retirement register file into addressable entries of a retirement array.

1 more element

A method of renaming a current set of logical registers to physical registers, said logical registers associated with a current set of operations, said method comprising the steps of:

providing a retirement register file for maintaining register values stored by nonspeculative operations;
renaming said logical registers to said physical registers upon issuance of said current set of operations, wherein said step of renaming comprises the steps of:
storing pointers to said physical registers into addressable entries of a RAT array memory corresponding to said logical registers;
and providing stack valid bits for indicating if valid data is pointed to by said addressable entries of said RAT array memory;
and
updating a retirement register ordering of registers within said retirement register file upon retirement of individual operations, wherein said step of updating said retirement register ordering comprises the steps of:
storing pointers to individual registers of said retirement register file into addressable entries of a retirement RAT array memory;
and providing retirement stack valid bits for indicating if valid data is pointed to by said addressable entries of said retirement RAT array memory.

5 more elements

A microprocessor comprising:

a bus interface unit for interfacing with a bus means;
instruction decode and fetch means coupled to said bus interface unit for decoding a current set of speculative operations for a given cycle;
execution units for simultaneously executing a set of speculative operations;
and
a means for renaming a current set of logical registers associated with said current set of speculative operations comprising:
a retirement register file means for maintaining register values stored by non-speculative operations;
array means for renaming said logical registers of said current set of logical registers to physical registers, said array means comprising a plurality of addressable entries corresponding to individual logical registers, said plurality of addressable entries for storing pointers to individual physical registers;
retirement array means for maintaining a retirement register ordering of registers within said retirement register file means, said retirement array means comprising a plurality of addressable entries for storing pointers to individual registers of said registers of said retirement register file means;
and
means for updating said array means based on issuance of said current set of speculative operations;
and
means for updating said retirement array means based on nonspeculative retiring operations.

9 more elements

A computer system comprising:

a bus means for providing communication interface;
memory means coupled to said bus means for storing instructions and computer data;
interface means coupled to said bus means for providing data input and data output to interface with a user;
and
microprocessor means coupled to said bus means for executing instructions and processing computer data, said microprocessor means further comprising a means for renaming a current set of logical registers associated with a current set of operations comprising:
a retirement register file means for maintaining register values stored by non-speculative operations;
array means for renaming said logical registers of said current set of logical registers to physical registers, said array means comprising a plurality of addressable entries corresponding to individual logical registers, said plurality of addressable entries for storing pointers to individual physical registers;
retirement array means for maintaining a retirement register ordering of registers within said retirement register file means, said retirement array means comprising a plurality of addressable entries for storing pointers to individual registers of said registers of said retirement register file means;
and
means for updating said array means based on issuance of said current set of operations which are speculative operations;
and
means for updating said retirement array means based on retiring operations which are non-speculative.

9 more elements

Dependencies are inferred from the claim text.

Floating point register alias table FXCH and retirement floating point register array

Life of this patent

Floating point register alias table FXCH and retirement floating point register array

Life of this patent

Abstract

Claims51