Arrangement of detecting branch error in a digital data processing system

A hardware arrangement for detecting a branch error in a program previously stored in a memory, comprising:

• first means for receiving said program from said memory and further receiving a first signal, said program including an entry point instruction embedded therein at an entry point where control is transferred to new program flow, said first means successively decoding a plurality of program instructions of said program and generating decoded program instructions therefrom, said first means further generating a second signal, said second signal indicating whether or not a program instruction just decoded is a branch instruction;
• and
• second means, coupled to receive said second signal, for storing said second signal, said second means applying said second signal to said first means as said first signal at a next cycle,
• wherein said first means generates a third signal indicating a branch error when said first means decodes an entry point instruction indicating that control has been transferred to new program flow and said first signal indicates that a program instruction previously decoded is not a branch instruction.